LDPC Decoder LLR Saturation for Faster Error Correction
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Solution Overview
Problem
Current LDPC decoders in wired local area networks, such as Ethernet, face challenges in achieving low bit error rates (BER) while maintaining low power consumption, as they require numerous iterations for error correction, leading to higher power consumption and longer processing times.
Innovation Solution
The proposed solution involves saturating the log-likelihood ratio (LLR) values of known bits in an LDPC frame to the highest possible magnitude, allowing for quicker convergence and improved error correction without increasing power consumption, by passing these values between check nodes and message nodes within the decoder.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional LDPC decoders perform multiple iterations for error correction, then bit error rate improves, but power consumption increases
Solution Approach 1:
The patent applies preliminary action by pre-saturating the LLR values of known bits (such as parity bits and known data bits) to their maximum magnitude before the decoding process begins. This preliminary saturation provides strong initial guidance to the decoder, enabling it to converge to the correct solution in fewer iterations and thereby reducing power consumption while maintaining low bit error rates.
Solution Approach 2:
The patent changes the parameter values of LLR (log-likelihood ratio) messages for known bits by saturating them to maximum magnitude. This parameter modification creates a stronger signal for the decoder to follow, accelerating convergence and reducing the number of iterations required, thus resolving the contradiction between reliability and power consumption.
2Reliability
If conventional LDPC decoders perform multiple iterations for error correction, then bit error rate improves, but processing time increases
Solution Approach 1:
By pre-saturating LLR values of known bits before decoding, the patent enables the decoder to converge faster, reducing the number of iterations needed and thereby decreasing processing time while still achieving low bit error rates.
Solution Approach 2:
The saturation of LLR parameters for known bits creates a stronger initial signal that guides the decoding process more efficiently, reducing the time required to achieve convergence without sacrificing error correction performance.
3Use of energy by moving object
If LDPC decoder reduces iterations to lower power consumption, then power savings increase, but error correction capability deteriorates
Solution Approach 1:
The patent reconciles this contradiction by performing preliminary saturation of known bit LLR values, which provides the decoder with strong initial information. This allows the system to use fewer iterations (reducing power consumption) while maintaining effective error correction capability through the enhanced initial guidance signal.
Solution Approach 2:
By changing the LLR parameter values for known bits to maximum magnitude, the patent creates a stronger guiding signal that enables effective error correction with fewer iterations, thus achieving both low power consumption and maintained error correction capability.
4Productivity
If LDPC decoder reduces iterations to decrease processing time, then speed improves, but error correction capability deteriorates
Solution Approach 1:
The patent achieves high processing speed with maintained error correction capability by pre-saturating LLR values of known bits. This preliminary action provides strong initial guidance that enables the decoder to converge quickly (high speed) while still achieving effective error correction.
Solution Approach 2:
The saturation of LLR parameters for known bits creates a stronger initial signal that guides the decoding process more efficiently, enabling fast convergence (improved productivity) without sacrificing error correction performance.
Data Source
AI summary
Reduced complexity decoders with improved error correction and related systems, methods, and apparatuses are disclosed. An apparatus includes an input terminal and a processing circuitry. The input terminal is provided at a physical layer device to receive, from a network, a low density parity check (LDPC) frame including bits. The bits correspond to log-likelihood ratio (LLR) messages indicating probabilities that the bits have predetermined logic values. The processing circuitry is to saturate LLR values of a portion of the LLR messages corresponding to known bits of the LDPC frame to a highest magnitude value represented by the LLR messages, and pass the LLR messages between check nodes and message nodes. The message nodes correspond to the bits. The check nodes correspond to parity check equations of a parity check matrix.