LDPC Decoder LLR Buffering and PCM Scheduling for Higher Throughput
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Solution Overview
Problem
Existing decoding hardware for low-density parity-check (LDPC) codes faces challenges in minimizing memory requirements and optimizing processing schedules to reduce pipeline conflicts and stall cycles, which affects throughput and hardware efficiency.
Innovation Solution
The proposed solution involves a decoder architecture that uses a hybrid decoding algorithm and an optimized processing schedule for the parity check matrix, which includes a double buffering mechanism to ensure that the latest LLR values are buffered and used for updates, reducing the need for patch LLRs and minimizing memory requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a layered decoding schedule is used to process the parity check matrix in parts, then faster convergence is achieved, but pipeline conflicts and stall cycles increase, reducing throughput
Solution Approach 1:
The decoder dynamically switches between layered decoding mode (for faster convergence) and flooding decoding mode (for continuous processing without stall cycles). The controller monitors pipeline conflict conditions and adjusts the decoding schedule in real-time, allowing the system to adapt its processing mode based on current operational needs, thus resolving the contradiction between convergence speed and throughput.
Solution Approach 2:
The patent changes the processing parameters of the parity check matrix by reorganizing the layered structure and adjusting the number of layers processed in each stage. By optimizing these parameters, the decoder reduces pipeline conflicts while maintaining fast convergence, and can switch to flooding mode when parameter optimization is insufficient, thereby balancing both convergence and throughput requirements.
2Device complexity
If the LLR memory capacity is reduced to minimize hardware requirements, then memory utilization improves, but pipeline conflicts increase due to insufficient buffering of latest LLR values
Solution Approach 1:
The LLR memory is segmented into multiple banks or regions, allowing selective access to different portions of the memory. This segmentation enables the decoder to manage limited memory resources more efficiently by only buffering the necessary latest LLR values for current processing, rather than maintaining full buffering capacity, thus reducing overall memory requirements while maintaining decoding accuracy.
Solution Approach 2:
The patent introduces an intermediary buffer or register structure between the LLR memory and the processing units. This intermediary holds the critical latest LLR values temporarily, allowing the main LLR memory to be smaller while still providing timely access to updated values, thus resolving the conflict between memory size and decoding reliability.
3Reliability
If the number of patch LLRs buffered is increased to resolve pipeline conflicts, then decoding accuracy improves, but memory requirements and hardware complexity increase
Solution Approach 1:
Instead of buffering all possible patch LLRs, the patent implements partial buffering by selectively identifying and buffering only the critical patch LLR values that are necessary for resolving pipeline conflicts in the current processing stage. This partial action approach achieves sufficient decoding accuracy without the excessive hardware complexity of complete buffering.
Solution Approach 2:
The patent dynamically adjusts the number of patch LLRs buffered based on processing stage and conflict conditions. By changing this parameter adaptively rather than maintaining a fixed large buffer, the system achieves high decoding accuracy when needed while reducing hardware complexity during normal operation, thus resolving the contradiction between reliability and device complexity.
Data Source
AI summary
The disclosure generally relates to improvements of a log-likelihood ratios (LLRs) memory structure and memory capacity of a decoding hardware (also referred to as a decoder) in decoding a sequence of codewords encoded with a low-density parity-check (LDPC) code (e.g. a quasi-cyclic (QC) LDPC code). Further, the disclosure relates to the optimization of a processing schedule of a parity check matrix (PCM) describing the LDPC code so as to reduce or minimize the number of patch LLRs that need to be (simultaneously) stored in an LLR memory of a decoder.