LDPC Decoder LLR Transformation for Lower Toggling Power
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing LDPC decoders in optical communication systems consume high power due to frequent toggling during iterative decoding processing, which is not efficiently managed by conventional methods.
Innovation Solution
The implementation of a low-density parity-check (LDPC) decoder architecture comprising a pre-processor, core decoder, and post-processor, where the pre-processor transforms received log-likelihood-ratio (LLR) sequences into a form that reduces toggling rates, and the post-processor applies complementary transformations to recover the codeword, thereby optimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional LDPC decoding processing is performed without transformation, then decoding accuracy is maintained, but power consumption increases due to frequent toggling
Solution Approach 1:
The pre-processor performs sign-bit flipping on LLR values before they enter the core decoder. This preliminary transformation modifies the input data to reduce subsequent toggling activity in the decoder circuits, achieving power savings without affecting final decoding accuracy. The transformation is reversible through the post-processor which applies complementary transformations to recover the original codeword.
Solution Approach 2:
The LDPC decoder is divided into three functional segments: a pre-processor that transforms LLR sequences, a core decoder that performs iterative decoding with reduced toggling, and a post-processor that recovers the original codeword. This segmentation allows each component to be optimized for its specific function, with the pre-processor handling power optimization and the post-processor ensuring accuracy.
2Reliability
If iterative decoding processing is performed with frequent toggling, then decoding accuracy is maintained, but power consumption increases
Solution Approach 1:
Instead of directly decoding the received LLR sequence, the pre-processor inverts certain sign bits of the LLR values based on a predetermined pattern. This inversion transforms the decoding problem into an equivalent form that achieves the same decoding accuracy but with reduced toggling activity in the core decoder, thereby lowering power consumption.
Solution Approach 2:
The pre-processor modifies the parameters of the LLR sequence by flipping sign bits according to a specific pattern. This parameter transformation changes the statistical properties of the input data to the core decoder, reducing the variance in toggling behavior and enabling more consistent and lower power consumption during iterative decoding.
Data Source
AI summary
A low-density parity-check (LDPC) decoder comprising a pre-processor, a core decoder, and a post-processor. The pre-processor is configured to transform a received log-likelihood-ratio (LLR) sequence into a form that enables the core decoder to toggle at a reduced rate during iterative decoding processing thereof. Upon stoppage of the decoding processing corresponding to the LLR sequence, the post-processor operates to apply a complementary transformation to the output of the core decoder, which recovers the corresponding codeword of the LDPC code. An example embodiment of the LDPC decoder operating in this manner may be able to beneficially reduce the power consumption therein by about 10%.