LDPC Decoder LLR Transformation for Lower Switching Power
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Solution Overview
Problem
Conventional LDPC decoders in optical communications systems consume high power due to frequent toggling during iterative decoding, which is inefficient and costly for digital signal processors.
Innovation Solution
Implementing a pre-processor and post-processor in the LDPC decoder to transform LLR sequences into lower-toggle sign bit-words, using bias information to alter parity-check conditions, thereby reducing toggling rates and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional LDPC decoding is performed without transformation, then decoding accuracy is maintained, but power consumption is high due to frequent toggling
Solution Approach 1:
The pre-processor performs sign-bit flipping on LLR values before they enter the core decoder. This preliminary transformation modifies the input data to reduce subsequent toggling activity in the decoder, achieving power savings without compromising decoding accuracy. The transformation is reversible and maintains the integrity of the decoding process.
Solution Approach 2:
The invention applies sign-bit inversion to LLR values as a preprocessing step. By flipping the signs of LLR values according to specific patterns, the decoder encounters fewer transitions during iterative decoding, thereby reducing power consumption. The post-processor applies the inverse transformation to recover the correct codeword.
2Reliability
If iterative decoding is performed with frequent toggling, then decoding accuracy is achieved, but power consumption increases
Solution Approach 1:
The pre-processor transforms LLR values before decoding to minimize toggling during iteration. This preliminary action ensures that the core decoder operates with reduced switching activity while maintaining the ability to achieve accurate decoding results through the reversible transformation.
Solution Approach 2:
The invention changes the parameter representation of LLR values by flipping sign bits according to specific patterns. This parameter transformation reduces the toggling rate during iterative decoding while preserving the information needed for accurate decoding. The post-processor reverses this parameter change to obtain the final result.
Data Source
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AI summary
A low-density parity-check (LDPC) decoder comprising a pre-processor, a core decoder, and a post-processor. The pre-processor is configured to transform a received log-likelihood-ratio (LLR) sequence into a form that enables the core decoder to toggle at a reduced rate during iterative decoding processing thereof. Upon stoppage of the decoding processing corresponding to the LLR sequence, the post-processor operates to apply a complementary transformation to the output of the core decoder, which recovers the corresponding codeword of the LDPC code. An example embodiment of the LDPC decoder operating in this manner may be able to beneficially reduce the power consumption therein by about 10%.