LDPC Decoder Load Balancing for Throughput-Area Tradeoffs
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Solution Overview
Problem
Implementing multiple LDPC decoders in a decoding system increases circuit area and signal timing difficulties, especially for short codewords with lifting factors less than the maximum value, which affects decoding efficiency.
Innovation Solution
A decoding circuit system using a full range decoder and auxiliary decoders, with a load balancing scheduler to distribute codewords based on lifting factors, directing those above a predefined value to the full range decoder and those below to auxiliary decoders, optimizing hardware usage and throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple LDPC decoders are implemented in parallel to increase throughput, then decoding efficiency is improved, but circuit area increases and signal timing becomes more difficult to close
Solution Approach 1:
The patent segments the decoder population into different types: full-range decoders for maximum lifting factors and auxiliary decoders for smaller lifting factors. This segmentation allows the system to use smaller auxiliary decoders for the majority of short codewords, reducing overall circuit area while maintaining high throughput for mixed workloads.
Solution Approach 2:
The patent applies local quality by assigning different decoder configurations to different workload scenarios. Auxiliary decoders with reduced processing circuits are used locally for short codewords with small lifting factors, while full-range decoders are used for long codewords requiring maximum lifting factors, optimizing resource utilization for each specific case.
2Productivity
If multiple LDPC decoders are implemented in parallel to increase throughput, then decoding efficiency is improved, but signal timing difficulty increases
Solution Approach 1:
The patent segments decoders into auxiliary and full-range types with distinct timing characteristics. This segmentation allows the timing closure process to be divided into manageable subsets, where auxiliary decoder timing is optimized for short codewords and full-range decoder timing is optimized for long codewords, reducing overall timing complexity.
3Adaptability or versatility
If full range decoders are used for all codewords to ensure comprehensive decoding capability, then all lifting factors are supported, but circuit area is unnecessarily increased for short codewords
Solution Approach 1:
The patent segments the decoder functionality into auxiliary decoders that handle small lifting factors and full-range decoders that handle maximum lifting factors. This segmentation ensures that short codewords are processed by smaller auxiliary decoders, avoiding the unnecessary circuit area overhead of using full-range decoders for all codewords.
Solution Approach 2:
The patent applies local quality by matching decoder capability to codeword requirements. Auxiliary decoders with processing circuits sized for small lifting factors are assigned to short codewords, providing appropriate decoding capability without the excess circuit area that would result from using full-range decoders for all cases.
4Area of stationary object
If auxiliary decoders with fewer processing circuits are used to reduce circuit area, then throughput efficiency improves, but the ability to decode long codewords with maximum lifting factors is reduced
Solution Approach 1:
The patent segments the workload by lifting factor size, directing short codewords to auxiliary decoders and long codewords to full-range decoders. This segmentation allows auxiliary decoders to operate with reduced circuit area for the majority of short codeword traffic, while full-range decoders handle the minority of long codewords requiring maximum lifting factor support.
Solution Approach 2:
The patent creates a universal decoder system where both auxiliary and full-range decoders can process various codeword types, though with different performance characteristics. The load balancing scheduler dynamically assigns codewords to appropriate decoder types, ensuring that the system as a whole maintains full lifting factor support capability while optimizing area efficiency for mixed workloads.
Data Source
AI summary
A decoding circuit system includes a load balancing scheduler circuit, a full range decoder circuit, and an auxiliary decoder circuit. The load balancing scheduler circuit provides codewords that each have a lifting factor greater than a predefined value to the full range decoder circuit. The full range decoder circuit decodes the codewords that each have a lifting factor greater than the predefined value to generate first decoded output data. The load balancing scheduler circuit provides codewords that each have a lifting factor less than the predefined value to the auxiliary decoder circuit. The auxiliary decoder circuit decodes the codewords that each have a lifting factor less than the predefined value to generate second decoded output data.