LDPC Decoder Parallel Check-Node Updates for Low Latency
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Solution Overview
Problem
Current data storage devices face challenges in achieving high performance decoding of codewords with low latency and low complexity, which is essential for competitive data rates while minimizing power consumption and complexity.
Innovation Solution
The implementation of a low density parity check (LDPC) decoder system that includes a variable node processor, edge combiner, check node processor, and convergence checker circuit, which processes variable-to-check message vectors in parallel to update check node vectors and detect valid codewords efficiently, utilizing a flooding decoder architecture with high parallelism to reduce iteration time and power requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional sequential decoding methods are used, then decoding accuracy can be maintained, but latency and processing time increase
Solution Approach 1:
The codeword is divided into multiple blocks, with each block containing a subset of codeword bits. Multiple decoding operations are performed in parallel on different blocks simultaneously, allowing the decoder to process multiple segments of the data concurrently rather than sequentially, thereby reducing overall decoding latency while maintaining accuracy through multiple parallel decoding attempts
Solution Approach 2:
The decoder performs a limited number of decoding iterations (e.g., up to 3 iterations per block) on each block before moving to the next block, rather than exhaustively completing all possible iterations for one block before proceeding. This partial action approach allows parallel processing of multiple blocks to overlap in time, reducing total latency while achieving sufficient decoding accuracy through the combination of multiple partial decoding results
2Productivity
If high parallelism is implemented to reduce latency, then decoding speed improves, but power consumption and complexity increase
Solution Approach 1:
By segmenting the codeword into multiple smaller blocks that can be decoded in parallel, the system achieves higher throughput and decoding speed. The parallel decoding of multiple blocks simultaneously increases productivity without requiring the entire decoder infrastructure to operate at maximum capacity continuously, thereby managing power consumption more efficiently through distributed parallel processing rather than monolithic high-power operation
Solution Approach 2:
The decoder employs periodic iterative decoding attempts on each block (e.g., up to 3 iterations) rather than continuous exhaustive decoding. This periodic action allows the system to periodically check for convergence and stop early when successful, reducing average power consumption per block while maintaining high overall decoding speed through the parallel processing of multiple blocks at different stages of their decoding periodic cycles
3Reliability
If multiple decoding iterations are performed to improve accuracy, then error correction capability increases, but latency and complexity increase
Solution Approach 1:
The codeword is segmented into multiple blocks, and multiple decoding iterations are performed on each block in parallel. This segmentation allows the system to distribute the computational complexity across multiple independent parallel decoding operations rather than one complex sequential process, maintaining high error correction capability through multiple iterations while managing overall system complexity through parallelization and early termination when convergence is achieved
Data Source
AI summary
Systems and methods are disclosed for implementing a low latency decoder. In certain embodiments, an apparatus may comprise decoder configured decode a codeword of bits, including: a variable node processor configured to provide a plurality of variable-to-check (v2c) message vectors to the edge combiner in parallel, the plurality of v2c message vectors including estimates for a selected set of bits of the codeword; the edge combiner configured to generate a plurality of output message vectors for a plurality of check node vectors based on the plurality of v2c message vectors, and provide the plurality of output message vectors to the plurality of check node vectors simultaneously; a check node processor configured to update the plurality of check node vectors based on the plurality of output message vectors; and a convergence checker circuit configured to detect a valid code word based on bit value estimates from the variable node processor.