LDPC Decoder Parallel Hard/Soft Decisions for Lower Latency
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Solution Overview
Problem
Low density parity check (LDPC) codes exhibit significant decoder latency due to the need to receive the entire block before decoding can start, which increases overall latency and processing time, especially with multiple iterations required for decoding.
Innovation Solution
A method and system that generate error detection codewords and systematic error correction codewords, allowing for parallel processing of soft and hard bit decisions to determine reliable source bits, enabling early output of reliable data without waiting for full decoding, and optionally using LDPC encoders for encoding and decoding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional LDPC decoding is used, then error correction capability is maintained, but decoder latency increases significantly
Solution Approach 1:
The patent segments the LDPC block into multiple sub-blocks and processes them in parallel using multiple decoding paths. Each path handles a portion of the data, allowing early termination when sufficient reliability is achieved, thus reducing overall decoding latency while maintaining error correction capability.
Solution Approach 2:
The patent implements dynamic decoding by allowing the decoding process to terminate early when a confidence threshold is met, rather than always completing full iterations. The system adapts the decoding depth based on channel conditions and data reliability, reducing average latency while preserving reliability when needed.
2Measurement precision
If full LDPC block reception is required before decoding, then decoding accuracy is improved, but processing time increases
Solution Approach 1:
The patent performs preliminary decoding on received sub-blocks before the entire LDPC block is received. By processing available data early and using confidence metrics to assess reliability, the system can make preliminary decisions without waiting for complete block reception, reducing processing time while maintaining adequate accuracy.
Solution Approach 2:
The patent uses feedback from confidence metrics and decoding results to dynamically adjust the decoding process. When confidence thresholds are met, the system terminates early; when confidence is low, it continues processing. This feedback mechanism balances accuracy requirements with time efficiency.
3Reliability
If multiple decoding iterations are performed, then error detection capability is improved, but latency increases
Solution Approach 1:
The patent implements dynamic iteration control where the number of decoding iterations is adjusted based on channel conditions and data characteristics. The system performs multiple iterations only when necessary (low confidence) and terminates early when confidence is high, maintaining error detection capability while reducing average latency.
Solution Approach 2:
The patent applies partial decoding iterations based on confidence thresholds. Instead of always performing the full number of iterations, the system performs only the necessary portion needed to achieve adequate confidence, reducing unnecessary processing time while maintaining sufficient error detection capability.
Data Source
AI summary
Encoding and decoding systems are provided for reduced latency at the decoder. In the encode error detection codewords are produced from source bits. The error detection codewords are then encoded with a systematic error correction encoder to produce a set of parity bits. All of the systematic code source bits and at least some of the parity bits are mapped to modulation symbols for transmission. In the decoder, two signal processings are performed in parallel, one based on soft bit decisions and the other based on hard bit decisions. The soft bit decisions are processed using a systematic error correction decoder. The hard bit decisions are processed by re-encoding error detection codewords to produce parity bits. If the produced parity bits match received parity bits, then the hard bit decisions are reliable and are output without waiting for the result of the systematic error correction decoder.