LDPC Decoder Memory Compression Using Error Bit Pointers
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Solution Overview
Problem
Current decoder memory solutions for solid state drives (SSDs) require significant resources in terms of power consumption, heat generation, silicon area, and cost due to the need for large SRAM to store error vectors during LDPC decoding operations.
Innovation Solution
A compression technique is employed to reduce the size of the decoder memory by storing only pointers to bit locations in error vectors, utilizing a probability distribution function to determine the necessary memory cells required, allowing for a smaller SRAM footprint and accommodating overflow when necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large SRAM is used to store error vectors during LDPC decoding operations, then error correction capability is maintained, but power consumption increases
Solution Approach 1:
The patent extracts only the essential information from error vectors by identifying and storing only the positions of '1' bits (error locations) rather than storing the entire error vector. This extraction principle reduces the memory storage requirement from storing all bits to storing only the positions of significant bits, thereby reducing power consumption while maintaining error correction capability.
Solution Approach 2:
Instead of storing the error vector directly as traditionally done, the patent inverts the approach by storing the complement information - specifically, the positions where bits equal '1' rather than storing all bit values. This inversion transforms the storage problem from storing dense data to storing sparse position information, reducing memory requirements and power consumption.
2Reliability
If large SRAM is used to store error vectors during LDPC decoding operations, then error correction capability is maintained, but heat generation increases
Solution Approach 1:
The patent extracts only the essential information from error vectors by identifying and storing only the positions of '1' bits (error locations) rather than storing the entire error vector. This extraction principle reduces the memory storage requirement from storing all bits to storing only the positions of significant bits, thereby reducing heat generation while maintaining error correction capability.
Solution Approach 2:
Instead of storing the error vector directly as traditionally done, the patent inverts the approach by storing the complement information - specifically, the positions where bits equal '1' rather than storing all bit values. This inversion transforms the storage problem from storing dense data to storing sparse position information, reducing memory requirements and heat generation.
3Reliability
If large SRAM is used to store error vectors during LDPC decoding operations, then error correction capability is maintained, but silicon area increases
Solution Approach 1:
The patent extracts only the essential information from error vectors by identifying and storing only the positions of '1' bits (error locations) rather than storing the entire error vector. This extraction principle reduces the memory storage requirement from storing all bits to storing only the positions of significant bits, thereby reducing silicon area while maintaining error correction capability.
Solution Approach 2:
Instead of storing the error vector directly as traditionally done, the patent inverts the approach by storing the complement information - specifically, the positions where bits equal '1' rather than storing all bit values. This inversion transforms the storage problem from storing dense data to storing sparse position information, reducing memory requirements and silicon area.
4Reliability
If large SRAM is used to store error vectors during LDPC decoding operations, then error correction capability is maintained, but cost increases
Solution Approach 1:
The patent extracts only the essential information from error vectors by identifying and storing only the positions of '1' bits (error locations) rather than storing the entire error vector. This extraction principle reduces the memory storage requirement from storing all bits to storing only the positions of significant bits, thereby reducing cost while maintaining error correction capability.
Solution Approach 2:
Instead of storing the error vector directly as traditionally done, the patent inverts the approach by storing the complement information - specifically, the positions where bits equal '1' rather than storing all bit values. This inversion transforms the storage problem from storing dense data to storing sparse position information, reducing memory requirements and cost.
Data Source
AI summary
Provided are an apparatus, storage device, and method for compressing error vectors for decoding logic to store compressed in an decoder memory used by the decoding logic. A decoder decodes codewords to produce error vectors used to decode the codewords. A decoder memory device stores the error vectors. A compression unit receives the error vector from the decoder during decoding of the codeword. Each bit in the error vector has one of a first value and a second value. A determination is made of at least one bit location in the error vector having the first value. At least one pointer is stored in a row of memory cells in the decoder memory device indicating the determined at least one bit location in the codeword having the first value.