Layered LDPC Decoder Pipelining for Memory Conflict Mitigation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current wireless communication systems face challenges in achieving high-throughput decoding for low-density parity-check (LDPC) codes due to processing delays and memory conflicts, particularly in deeply-pipelined architectures, which affect the efficiency and reliability of error correction in high-speed data transmission.
Innovation Solution
The implementation of a deeply-pipelined layered LDPC decoder architecture that relaxes the dependency between bit log likelihood ratios (LLRs) and a posteriori LLRs, along with techniques to resolve memory conflicts and consistency errors, enables faster processing and improved memory bandwidth, thereby enhancing decoding throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a deeply-pipelined LDPC decoder architecture is implemented to increase decoding speed, then processing throughput is improved, but processing delays and memory conflicts increase
Solution Approach 1:
The decoder architecture is segmented into multiple independent pipeline stages, each handling specific decoding operations. This segmentation allows parallel processing of different code blocks simultaneously, increasing throughput while managing processing delays through staged computation. The pipeline is divided into stages including LLR computation, check node processing, and bit node processing, which can operate concurrently on different data segments.
Solution Approach 2:
The patent introduces a time dimension to the decoding process by implementing deep pipelining, transforming a sequential single-cycle decoding approach into a multi-stage time-expanded architecture. This dimensional transformation allows multiple decoding operations to overlap in time, achieving high throughput while maintaining manageable processing delays through careful stage timing and synchronization.
2Productivity
If memory bandwidth is increased to support high-throughput decoding, then decoding efficiency is improved, but device complexity and cost increase
Solution Approach 1:
Log-likelihood ratios (LLRs) are pre-computed and stored in memory before the main decoding process begins. This preliminary action allows the decoder to retrieve pre-prepared data during pipeline operation, reducing real-time computational memory access requirements and bandwidth demands during critical decoding stages.
Solution Approach 2:
The patent introduces intermediate buffer memories and registers between pipeline stages to decouple memory bandwidth requirements from processing speed. These intermediary storage elements act as buffers that can be accessed at different rates by adjacent pipeline stages, allowing high throughput without proportionally increasing memory bandwidth requirements.
Data Source
Figure 1~2
Figure 3
Figure 4A
AI summary
Certain aspects of the present disclosure generally relate to methods and apparatus for decoding low density parity check (LDPC) codes, and more particularly to a deeply-pipelined layered LDPC decoder architecture for high decoding throughputs solving memory consistency and conflict problems. Aspects of the present disclosure present techniques for mitigating pipeline delays, for example, by relaxing the dependency between updating bit LLRs and computing check node messages, so that for a particular row, the check node processing can use the latest available bit LLR's (e.g., outdated bit LLRs) rather than waiting for the latest updates (e.g., updated bit LLRs) to occur. Memory consistency conflicts are avoided by storing the latest available bit LLRs in a LLR memory and updating the bit LLRs with the difference between old and new check node messages. Furthermore, logically splitting the LLR memory into dual banks enables the decoder to read or write from both banks of memory at the same time, thereby increasing the read/write bandwidth. Advantageously choosing the parity check matrix row (PCM) calculation order, sorting the check node messages and the bit LLR updates in memory, and/or choosing a memory bank to store the check node messages and bit LLR updates based on, for example, dependencies between rows in the PCM alleviates memory conflicts/consistency errors and reduces pipeline processing delays.