LDPC Decoder Memory Control Using Transfer-Gate Cell Selection
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Solution Overview
Problem
Existing analog decoders for LDPC codes face challenges in reducing combinational control logic, circuit area, and power consumption, particularly for codes with block off-diagonal structure, which affects their efficiency and performance.
Innovation Solution
The implementation of controllable transfer gates and co-located control logic within memory cells, along with a memory control circuitry that generates phase and cycle control signals to manage memory operations in an iterative process, reduces the complexity of sequencing and power consumption by effectively selecting memory cells in read or write modes, and optimizing the memory architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If controllable transfer gates and co-located control logic are implemented in memory cells, then device complexity is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent co-locates control logic within each memory cell, merging previously separate control functions with storage elements. This integration eliminates the need for extensive external combinational control logic, directly reducing device complexity while requiring precise manufacturing to ensure proper cell operation.
Solution Approach 2:
Each memory cell is equipped with its own control logic, enabling self-service operation without requiring complex external control circuits. The control logic within each cell autonomously manages read/write operations based on control signals, reducing overall system complexity.
2Productivity
If memory control circuitry with multiple selectors is used to manage iterative decoding, then productivity is improved, but device complexity increases
Solution Approach 1:
The memory control circuitry is segmented into multiple control signal selectors, each responsible for specific memory sections. This segmentation allows parallel control of different memory regions, improving memory operation efficiency and productivity while distributing the control complexity across multiple manageable units.
Solution Approach 2:
The control signal selectors are designed with universal functionality to handle multiple phases and cycles of iterative decoding. Each selector can route different control signals to appropriate memory sections based on the current decoding phase, enabling a single control structure to manage complex iterative operations efficiently.
3Productivity
If phase and cycle control signals are generated for each memory section, then productivity is improved, but use of energy increases
Solution Approach 1:
The decoding process is organized into periodic phases and cycles, with control signals generated only when needed for each phase transition. This periodic control approach enables fast iterative decoding by systematically cycling through memory sections, improving productivity while managing power consumption through rhythmic rather than continuous signal generation.
Data Source
AI summary
A decoder control makes use of controllable transfer gates, which effectively implement selectors, to implement required timing offsets for codes that have particular structure. For instance, such timing offsets are effective for LDPC codes with block off-diagonal structure, for instance, as described in the co-pending application. In some implementations, the memory architecture is formed of cells where each cell includes not only a storage element, by also control logic that combines a select signal and the write versus read signal. By co-locating this control logic in each memory cell, control logic and its associated signal distribution is reduced, thereby reducing circuit area and power consumption.