LDPC Decoder Memory Layout for Higher-Throughput Message Updating
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Solution Overview
Problem
Existing decoders for memory systems, particularly in solid state drives, face challenges in optimizing throughput and degree-of-freedom due to the use of first-in, first-out (FIFO) memory for message updating, which complicates control and hinders subsequent optimization, especially in low-density parity check codes.
Innovation Solution
A decoder design that includes a posterior probability storage module, node message storage module, and message updating module, utilizing random access memory units to store and update messages in a specific order, allowing for sequential output and simplifying the control process, thereby improving throughput and degree-of-freedom.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If FIFO memory is used for message updating in existing decoders, then message updating can be performed, but control complexity increases and optimization is hindered
Solution Approach 1:
The patent extracts the message updating function from the FIFO memory control structure and implements it using separate random access memory units with independent read and write pointers. This separation eliminates the complex control logic required for FIFO operations while maintaining the message updating functionality, directly reducing control complexity.
2Productivity
If FIFO memory is used for message updating, then message storage is enabled, but throughput and degree-of-freedom optimization is hindered
Solution Approach 1:
The patent segments the message storage function into multiple independent random access memory units, each handling specific message types (e.g., check-to-variable messages, variable-to-check messages). This segmentation allows parallel access and updating operations, improving throughput while simplifying the control degree-of-freedom compared to a unified FIFO structure.
Solution Approach 2:
The patent implements dynamic message updating by allowing independent read and write operations on the same memory units during the same decoding iteration. This dynamic access pattern, enabled by separate read and write pointers, increases the degree-of-freedom for optimization while improving throughput through concurrent operations.
3Productivity
If sequential output in different order is implemented, then decoding efficiency is improved, but memory access patterns become more complex
Solution Approach 1:
The patent introduces intermediate buffer memory units that temporarily store messages before final output. These buffer units act as mediators between the computational units and the final output stage, allowing results to be produced in any desired order without complicating the core computational memory access patterns. The buffers absorb the reordering complexity while maintaining simple access patterns in the critical path.
Data Source
AI summary
According to one aspect, the present disclosure provides a decoder. The decoder may include a posterior probability storage module that stores a posterior probability message respectively corresponding to each of a plurality of cyclic permutation matrices. The decoder may include a node message storage module that stores a message transmitted to a variable node by a check node respectively corresponding to each of the plurality of cyclic permutation matrices. The decoder may include a message updating module that sequentially receives the posterior probability message and the message transmitted to the variable node by the check node respectively corresponding to each of the plurality of cyclic permutation matrices in a first order, and sequentially outputs the updated message transmitted to the variable node by the check node and an updated posterior probability message respectively corresponding to each of the plurality of cyclic permutation matrices in a second order.