LDPC Decoder Memory Shifting for More Iterations per Frame
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Solution Overview
Problem
Current low density parity check (LDPC) error correction systems in satellite communications face limitations in processing capacity and efficiency due to structural constraints, such as memory allocation and memory access processing, which restrict the number of iterations that can be performed within a given timeframe, affecting decoder performance.
Innovation Solution
An error correction system with a main memory, a switch to select between two processors, and a controller for controlling data processing and memory operations, including forward and reverse shift operations to reorder data efficiently, allowing for increased iterations and improved resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional memory allocation and processing methods are used in LDPC decoders, then the system structure is simpler, but the number of iterations that can be performed within a given timeframe is limited
Solution Approach 1:
The patent divides the LDPC decoder into multiple processing units (first processing unit, second processing unit, third processing unit) that can operate in parallel on different segments of the data stream. This segmentation enables multiple iterations to be performed simultaneously, increasing the total number of iterations within the frame time without requiring a single complex processing unit
Solution Approach 2:
The patent introduces a time-dimensional approach by implementing pipelined processing where different processing units work on different iterations simultaneously. The controller coordinates multiple processing units to perform iteration 1 on block 1, iteration 2 on block 2, etc., effectively adding a time dimension to the processing capability
2Productivity
If more processing units are added to increase iteration capacity, then the number of iterations increases, but the device size and power consumption increase
Solution Approach 1:
The patent designs processing units that can handle multiple functions: they can process different data blocks, perform different iterations, and switch between processing modes under controller direction. This multi-functionality allows a smaller number of versatile units to replace what would otherwise require many specialized units, reducing overall device size
Solution Approach 2:
The patent combines control functions for multiple processing units into a single controller that coordinates their operations. The controller manages data flow, switching between units, and coordination of iterations, merging what would otherwise be distributed control logic into a centralized management unit that reduces redundancy
3Productivity
If more processing units are added to increase iteration capacity, then the number of iterations increases, but power consumption increases
Solution Approach 1:
The patent implements a periodic processing scheme where processing units are activated in cycles rather than continuously. The controller enables processing units to work on different iterations in a periodic fashion, allowing idle units to enter low-power states while maintaining high overall iteration throughput
Solution Approach 2:
The patent creates a dynamic processing architecture where the controller can adaptively activate or deactivate processing units based on the current iteration requirements and data availability. This dynamic control allows the system to optimize power consumption by activating only the necessary number of units at any given time rather than running all units continuously
Data Source
AI summary
The disclosed embodiments relate to an apparatus and method for decoding signals in a receiver, such as signals using low density parity check error correction. The apparatus includes a link circuit. The link circuit may include a first memory, a first and second processing block, and also include a first shift circuit for shifting data before entering one of the processing blocks and a second shift circuit for reversing the first shift after exiting the processing block. The link circuit may also include a second memory used for intermediate storage and shared by the first and second processing block. The method includes reading data from a memory, shifting the data prior to processing, processing the data, and then reverse shifting the data prior to writing it back to the memory.