LDPC Decoder Memory Switching to Avoid Data Collision

The patent merges multiple switching networks into a single switching network that handles both writing and reading operations. The switching network is configured to dynamically route data between calculation units and memory blocks, eliminating the need for separate switching networks for write and read operations. This consolidation reduces circuit area while maintaining the parallel processing capability through time-multiplexed access to memory blocks.

The patent introduces dynamic control of the single switching network to adaptively allocate memory block access between writing and reading operations. The switching network dynamically changes its configuration based on the current operation phase, allowing the system to maintain high computing parallelism without requiring static dedicated paths for each operation type. This dynamic approach prevents data collision by ensuring only one operation type accesses a given memory block at any moment.

The patent employs dynamic control of the single switching network to prevent data collision by ensuring that at any given time, a memory block is dedicated to either writing or reading operations, but not both simultaneously. The switching network dynamically reconfigures itself based on the current operation phase, creating temporal separation between write and read accesses to the same memory block. This dynamic time-multiplexing approach maintains high computing parallelism while eliminating data collision risks.

The single switching network acts as an intermediary between calculation units and memory blocks, mediating all data access requests. It intelligently routes write operations and read operations through appropriate paths, preventing direct conflict between simultaneous write and read accesses to the same memory block. The switching network serves as a centralized controller that coordinates access timing to eliminate data collision while preserving parallel processing efficiency.