LDPC Decoder Self-Correction for Unreliable Message Handling
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Solution Overview
Problem
Non-binary low density parity-check (LDPC) codes face challenges in hardware implementation due to high decoding complexity and latency, which affects their performance in error correction, especially in applications requiring low frame error rates and high throughput.
Innovation Solution
The implementation of a dynamic self-correction mechanism that adjusts message reliabilities during the decoding process by detecting and reducing the influence of unreliable messages in Trellis-Extended Min-Sum decoders, improving the raw bit error rate (RBER) performance without significant additional hardware cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If non-binary LDPC codes are used for error correction, then error correction performance is improved, but decoding complexity increases
Solution Approach 1:
The patent applies parameter changes by using non-binary algebraic structures (GF(q) fields with q>2) instead of traditional binary structures. This changes the fundamental parameter of the code alphabet size, enabling better error correction performance while managing complexity through structured mathematical operations in finite fields.
Solution Approach 2:
The patent segments the decoding process into distinct functional modules: variable node processing units, check node processing units, and message passing pathways. This segmentation allows parallel processing of multiple messages simultaneously, reducing overall decoding complexity while maintaining non-binary error correction capabilities.
2Reliability
If non-binary LDPC codes are used for error correction, then error correction performance is improved, but decoding latency increases
Solution Approach 1:
The decoder is segmented into multiple parallel processing units that can simultaneously process different messages and iterations. This parallel architecture reduces decoding latency by eliminating sequential bottlenecks while maintaining the iterative non-binary decoding process needed for high error correction performance.
Solution Approach 2:
The patent implements preliminary action through pre-computed lookup tables for logarithmic operations and pre-configured message passing schedules. These preliminary preparations reduce the computational burden during actual decoding operations, thereby reducing latency without compromising error correction performance.
3Productivity
If hardware parallelization is increased to reduce latency, then decoding speed is improved, but device complexity increases
Solution Approach 1:
The patent employs universal processing units that can handle multiple message types and operations through configurable logic. These multi-functional units reduce the need for dedicated hardware for each specific operation, achieving high parallelization speeds while controlling overall hardware complexity through resource sharing.
Solution Approach 2:
The patent uses simplified copied structures for message storage and transmission across parallel processing elements. Instead of complex unique data structures for each processing unit, standardized message formats and storage templates are copied and reused, reducing hardware complexity while enabling high-speed parallel operations.
Data Source
AI summary
An embodiment of an electronic apparatus comprises one or more substrates, and logic coupled to the one or more substrates, the logic to detect unreliable messages between check nodes and variable nodes in association with an error correction operation, determine respective degrees of unreliability for the unreliable messages, and reduce an influence of the unreliable messages on the error correction operation, as compared to an influence of reliable messages between the check nodes and the variables nodes, based on the determined respective degrees of unreliability. Other embodiments are disclosed and claimed.