LDPC Decoder Message Resolution for Power-Throughput Tradeoffs

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Solution Overview

Problem

Existing ECC decoders face challenges in optimizing the tradeoff between area, throughput, and power consumption due to constraints on silicon area, cost, power budget, error correction capability, and throughput requirements, particularly when supporting multiple decoding modes with different parallelism levels.

Innovation Solution

The solution involves setting the parallelism level of ECC decoders based on power consumption, frequency of use, and message resolution, and implementing transformations of the parity check matrix to enable different decoding modes to operate efficiently, allowing for hardware re-use and efficient multi-resolution processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple decoding modes with different parallelism levels are supported, then error correction capability is improved, but device complexity increases

Engineering Contradiction:

Improveerror correction capabilityVSAvoiddecoder complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The decoder is divided into multiple independent decoding modes (first decoding mode with high parallelism, second decoding mode with low parallelism), each capable of operating independently. This segmentation allows the system to select appropriate decoding capability based on error conditions without requiring all modes to be simultaneously active, thus managing complexity while maintaining error correction capability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The decoder dynamically transitions between different decoding modes based on decoding success or failure conditions. The control logic enables switching from the first decoding mode to the second decoding mode when needed, and vice versa, allowing the system to adapt its complexity level to the actual error conditions rather than maintaining fixed high complexity.

Inventive Principle:

Principle #15Dynamics

2Productivity

If high degree of parallelism is used in bit-flipping mode, then throughput performance is improved, but power consumption exceeds budget in soft decoding mode

Engineering Contradiction:

Improvethroughput performanceVSAvoidpower consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

Different parallelism levels are applied to different decoding modes based on their specific requirements. The first decoding mode (bit-flipping) uses high parallelism for maximum throughput, while the second decoding mode (soft decoding) uses low parallelism to control power consumption. Each mode has locally optimized quality characteristics suited to its function.

Inventive Principle:

Principle #3Local quality

3Use of energy by moving object

If both high-resolution and reduced-resolution soft decoding modes are supported, then power consumption is reduced in reduced-resolution mode, but decoder size and cost increase

Engineering Contradiction:

Improvepower consumptionVSAvoiddecoder size

Core Design Contradiction:

Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The decoder is designed with universal components that can function across multiple resolution modes. The same hardware infrastructure supports both high-resolution and reduced-resolution soft decoding modes, allowing the system to reduce power consumption by selecting reduced-resolution mode when appropriate, while avoiding the need for completely separate hardware for each mode.

Inventive Principle:

Principle #6Universality (Multi-functionality)

4Adaptability or versatility

If multiple sets of components are included to support multiple resolutions, then adaptability is improved, but manufacturing cost increases

Engineering Contradiction:

Improvemulti-resolution supportVSAvoidmanufacturing cost

Core Design Contradiction:

Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The decoder merges multiple resolution support into a single unified hardware structure. Rather than including separate complete sets of components for high-resolution and reduced-resolution modes, the design combines functionalities so that one set of components can operate in multiple resolution modes, reducing manufacturing cost while maintaining adaptability.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS10565040B2ECC decoder with selective component disabling based on decoding message resolution

Publication Date: 2020.02.18 SANDISK TECHNOLOGIES LLC

AI summary

A device includes a non-volatile memory and a low density parity check (LDPC) decoder configured to receive a representation of a codeword from the non-volatile memory. The LDPC decoder includes multiple data processing units (DPUs) and a control circuit coupled to the DPUs. The control circuit is responsive to an error metric associated with the representation of the codeword and is configured to set a message resolution at least partially based on the error metric and to selectively disable one or more components of the LDPC decoder based on the message resolution.