LDPC Decoder Layered Sub-Matrix Selection for MLC Read Reliability
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Solution Overview
Problem
In semiconductor memory systems, particularly in multi-level cell (MLC) non-volatile memory devices, the increasing number of bits programmed in each memory cell leads to decreased reliability and higher read failure rates due to overlapping threshold voltage distributions, resulting in significant bit errors during data reading.
Innovation Solution
A semiconductor memory system incorporating a Low-Density Parity Check (LDPC) decoder that selects sub-matrices sharing the same layer index, updates decision values by flipping bits based on a threshold value and unsatisfied check nodes, and iteratively performs syndrome checking and backup syndrome updates to correct errors and improve decoding accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of bits programmed in each memory cell is increased, then data storage capacity is improved, but reliability decreases and read failure rate increases
Solution Approach 1:
The parity check matrix is divided into multiple sub-matrices arranged in a grid structure with row indices and column indices. The decoding process segments the codeword into multiple parts corresponding to these sub-matrices, processing them in an ordered sequence rather than treating the entire codeword as a single block. This segmentation allows the decoder to systematically handle errors by processing different portions of the data through different sub-matrices.
Solution Approach 2:
The decoding process dynamically adjusts the processing based on syndrome check results. After each sub-matrix processing step, the syndrome is checked to determine if decoding is complete or if further processing is needed. The decoder dynamically selects which sub-matrix to process next based on the current decoding state and syndrome information, making the decoding process adaptive rather than static.
2Reliability
If error correction capability is enhanced to handle overlapping threshold voltage distributions, then reliability is improved, but decoding complexity increases
Solution Approach 1:
The parity check matrix is divided into multiple sub-matrices arranged in a grid structure with row indices and column indices. The decoding process segments the codeword into multiple parts corresponding to these sub-matrices, processing them in an ordered sequence rather than treating the entire codeword as a single block. This segmentation allows the decoder to systematically handle errors by processing different portions of the data through different sub-matrices.
Solution Approach 2:
The decoder processes sub-matrices in an ordered sequence based on row and column indices, performing partial decoding steps rather than attempting to decode the entire codeword simultaneously. The syndrome check is performed after each sub-matrix processing to determine if full decoding is achieved, allowing the system to stop early when successful rather than always completing all possible processing steps.
3Measurement precision
If iterative decoding operations are performed multiple times, then decoding accuracy is improved, but processing time increases
Solution Approach 1:
The decoding process uses periodic syndrome checks after processing each sub-matrix to determine whether to continue or terminate. Rather than performing a fixed number of iterations regardless of outcome, the system periodically evaluates the decoding state and stops when the syndrome indicates successful decoding, creating a rhythm of process-evaluate-continue-or-stop that balances accuracy and time.
Solution Approach 2:
The syndrome check provides feedback after each sub-matrix processing step, informing the decoder whether the current processing has achieved successful decoding. This feedback mechanism allows the system to adjust its behavior dynamically, continuing processing only when necessary and terminating early when the decoding goal is already met, thus optimizing the balance between accuracy and processing time.
Data Source
AI summary
A semiconductor memory system includes: a semiconductor memory device to store a codeword; and a low-density parity check (LDPC) decoder to decode the codeword, based on a parity check matrix, to generate a decoded codeword, wherein the LDPC decoder includes: a selector to select one or more sub-matrices that share the same layer index of the parity check matrix, and select variable nodes corresponding to columns included in the selected one or more sub-matrices based on a threshold value and a number of unsatisfied check nodes (UCNs) connected to the selected variable nodes; a variable node updater to update decision values of variable nodes corresponding to all columns included in the parity check matrix; a syndrome checker to determine whether decoding the codeword has been performed successfully or not; and a check node updater to update a backup syndrome, the threshold value, and a size of a processing unit.