LDPC Decoder Mode Switching for Irregular Node Degrees
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing LDPC decoders face inefficiencies in computational resource utilization due to varying degrees of variable nodes, leading to suboptimal throughput and decoding latency, particularly when dealing with irregular LDPC codes.
Innovation Solution
The LDPC decoder employs a mode controller to manage unit logic circuits in single and multi-mode operations, updating high-degree variable nodes sequentially and low-degree nodes in parallel, utilizing computational resources more efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the LDPC decoder sequentially updates variable nodes with varying degrees, then the decoding accuracy is maintained, but the computational resources are not fully utilized leading to reduced throughput
Solution Approach 1:
The patent applies dynamics by making the update mode of variable nodes adjustable based on their degree. The system dynamically switches between sequential update mode (for high-degree variable nodes) and parallel update mode (for low-degree variable nodes), allowing the decoder to adapt its computational resource allocation to the specific characteristics of each variable node, thereby fully utilizing available computational resources while maintaining decoding accuracy
Solution Approach 2:
The patent segments variable nodes into two categories based on their degree: high-degree variable nodes updated sequentially and low-degree variable nodes updated in parallel. This segmentation allows the system to apply different update strategies to different subsets of variable nodes, optimizing computational resource utilization for each group while maintaining overall decoding performance
2Productivity
If the LDPC decoder updates all variable nodes in parallel, then the throughput is increased, but the computational complexity increases and resources are wasted on high-degree nodes
Solution Approach 1:
The patent applies local quality by assigning different update modes to variable nodes based on their local characteristic (degree). Low-degree variable nodes are updated in parallel with full computational resources, while high-degree variable nodes are updated sequentially with reduced computational resources. This localized optimization ensures that computational complexity is appropriately matched to the actual needs of each variable node group, avoiding waste while maintaining throughput
Solution Approach 2:
The patent changes the operational parameter (update mode) of the LDPC decoder based on the degree parameter of variable nodes. By adjusting the update mode parameter between sequential and parallel based on the degree threshold, the system optimizes the balance between throughput and computational complexity for different variable node types
3Productivity
If the LDPC decoder uses a fixed update mode for all variable nodes, then the device complexity is reduced, but the decoding latency increases due to inefficient resource utilization
Solution Approach 1:
The patent reduces decoding latency by dynamically selecting update modes based on variable node degree. The mode controller automatically adjusts between sequential and parallel update modes, ensuring that computational resources are efficiently utilized for each variable node type. This dynamic adaptation minimizes unnecessary computational overhead while maintaining fast decoding speed, effectively reducing overall decoding latency
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A low density parity check (LDPC) decoder (100) initializing variable nodes with a value of a codeword and outputting the updated variable nodes as decoded messages with reference to an irregular parity check matrix. The LDPC decoder (100) includes a plurality of unit logic circuits (121, 122) operating in a single mode in which all the unit logic circuits (121, 122) update one variable node group including at least one variable node, or a multi-mode in which each of the unit logic circuits (121, 122) updates a plurality of variable node groups in parallel by updating different variable nodes, and a mode controller (113) controlling the plurality of unit logic circuits (121, 122) to update a high-degree variable node group having a degree greater than a threshold degree among the variable node groups in the single mode, and update a low-degree variable node group having a degree less than or equal to the threshold degree among the variable node groups in the multi-mode.