LDPC Decoder Node Compression for Lower Memory Die Area

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Solution Overview

Problem

Existing decoders for low-density parity-check (LDPC) codes require significant memory to store variable and check node states, which increases complexity and die area, but reducing the number of bits per node can degrade performance and limit the number of errors correctable.

Innovation Solution

Implementing a compression module to compress and store variable and check node information in a compressed format, using techniques such as lossy or lossless compression to reduce memory requirements while maintaining decoding performance, and utilizing bit flipping decoders with hybrid message-passing algorithms to efficiently update and decompress data.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If memory is increased to store variable and check node states, then decoding performance is improved, but die area and complexity increase

Engineering Contradiction:
Improvedecoding performanceVSAvoiddie area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent changes the representation parameters of node states by using exponential encoding where the magnitude of values is represented by the number of trailing zeros and the sign by the most significant bit. This parameter transformation allows the same decoding performance to be achieved with fewer memory bits, directly reducing die area while maintaining reliability.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent applies different storage strategies to different parts of the data structure. Variable nodes and check nodes use different memory allocation and encoding schemes based on their specific requirements. This localized optimization allows memory to be used more efficiently for each node type, reducing overall die area while maintaining the decoding performance required for each node's function.

Inventive Principle:
Principle #3Local quality

2Area of stationary object

If number of bits per node is reduced to decrease memory usage, then die area is reduced, but decoding performance and error correction capability are degraded

Engineering Contradiction:
Improvedie areaVSAvoiderror correction capability
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent transforms the parameter representation from storing actual magnitude values to storing encoded representations where trailing zeros indicate magnitude and the most significant bit indicates sign. This parameter change enables the same error correction capability to be maintained with fewer bits per node, directly addressing the contradiction between memory reduction and performance maintenance.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent creates a compressed representation (copy) of the node state information that preserves the essential decoding functionality. By copying only the critical sign information and deriving magnitude from the encoding structure itself, the system maintains error correction capability while using significantly fewer bits than storing complete magnitude values would require.

Inventive Principle:
Principle #26Copying

3Area of stationary object

If memory is reduced to store compressed node information, then die area and complexity are reduced, but memory access and update operations become more complex

Engineering Contradiction:
Improvedie areaVSAvoidcompression complexity
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The patent extracts only the essential information (sign bit and position of trailing zeros) from the complete node state representation. By taking out only the critical components needed for decoding and deriving the rest from the encoding structure, the system reduces memory size while keeping the compression and decompression logic relatively simple and manageable.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS9548764B1Memory efficient decoders for low-density parity-check codes
Publication Date: 2017.01.17 MARVELL ASIA PTE LTD
  • US9548764B1 patent drawing
  • US9548764B1 patent drawing
  • US9548764B1 patent drawing

AI summary

A decoder including a compression module configured to select one or more nodes from a plurality of nodes associated with data being decoded by the decoder, where each node includes one or more bits, and to compress the one or more bits associated with the selected nodes. A memory is configured to store the compressed one or more bits associated with the selected nodes.