LDPC Decoder Check-Node Gating for Lower Dynamic Power
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Solution Overview
Problem
Current LDPC decoders in communication systems experience high dynamic power consumption due to unnecessary updates of stable check nodes and bit nodes, especially in wireless standards like WiMax/WiBro, 802.11n, DVB-S2, and 10 Gbase-T, as they continue to update nodes even after message values have matured, leading to increased power usage.
Innovation Solution
A system and method that includes a sleep mode checking module and a gating circuit to identify and turn off Check Node and Bit Node Update Units (CNBNUs) when the absolute value of messages to bit nodes exceeds a threshold, thereby stopping unnecessary updates and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If check nodes and bit nodes are continuously updated for each iteration of message exchange, then decoding accuracy is improved, but dynamic power consumption increases
Solution Approach 1:
The patent applies dynamics by making the update operation conditional rather than static. The sleep mode checking module dynamically determines whether to perform updates based on real-time evaluation of message values against threshold criteria. This transforms the rigid continuous update mechanism into a flexible, adaptive process that adjusts operation based on actual decoding needs, thereby reducing unnecessary power consumption while maintaining decoding accuracy.
Solution Approach 2:
The patent changes the parameter of update frequency from constant to variable. By introducing threshold-based criteria that compare message values against predetermined limits, the system adjusts the update parameter dynamically. When message values exceed thresholds, updates are performed; when they remain within thresholds, updates are skipped. This parameter change enables the system to balance between decoding accuracy and power consumption based on actual message characteristics.
2Use of energy by moving object
If bit node gating scheme is implemented to turn OFF stable bit nodes, then dynamic power consumption is reduced, but device complexity increases due to additional memory blocks required for clock-gating circuit
Solution Approach 1:
The patent extracts the power consumption reduction function from the complex bit node gating scheme and relocates it to the check node level. Instead of gating individual bit nodes which requires extensive memory blocks and complex control logic, the invention gates entire check nodes based on their message evaluation. This extraction simplifies the device architecture by removing the need for complex bit-node-level clock-gating circuits while maintaining power reduction benefits.
Solution Approach 2:
The patent makes the sleep mode checking module a universal control mechanism that manages power for multiple check nodes simultaneously. Rather than implementing separate gating circuits for each bit node, a single sleep mode checking module evaluates messages and controls updates across numerous check nodes. This multi-functional approach reduces device complexity by consolidating control logic while maintaining the ability to reduce power consumption across the entire decoder.
3Use of energy by moving object
If threshold value is adjusted to reduce power consumption, then dynamic power consumption decreases, but decoding performance may be affected
Solution Approach 1:
The patent applies partial action by performing updates only when necessary, rather than continuously. The threshold-based mechanism allows the system to take partial updates—skipping updates when message values are stable and within thresholds, while performing updates only when values exceed thresholds indicating potential decoding improvements. This partial action approach reduces power consumption while maintaining sufficient decoding performance by focusing computational effort only where needed.
Data Source
AI summary
A system and method for reducing power consumption in a Low Density Parity-Check Code (LDPC) decoder includes a sleep mode checking module and a gating circuit. The sleep mode checking module checks whether a check node is in sleep mode. The check node is considered to be in sleep mode when the absolute value of the message going to each of the one or more bit nodes corresponding to the check node is greater than a threshold value. The gating circuit turns OFF a Check Node and Bit Node Update Unit (CNBNU) associated with the check node when the check node is in the sleep mode. Turning OFF a CNBNU stops the exchange of messages between the check node and its corresponding one or more bit nodes.