LDPC Decoder Node Grouping for High-Speed Low-Power Decoding
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Solution Overview
Problem
NAND flash-based storage devices require more powerful error correction codes due to increased noise and interference at smaller fabrication sizes, but handling these codes is computationally intensive and power-consuming.
Innovation Solution
Implementing a high-speed and power-efficient LDPC decoder by grouping variable nodes for separate updates, using a min-sum update algorithm that avoids calculating hyperbolic tangents, and optimizing message storage to reduce resource requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If LDPC codes are used to improve data integrity and overcome noise in NAND flash devices, then error correction capability is improved, but computing resources and power consumption increase
Solution Approach 1:
The patent divides variable nodes into multiple groups that can be updated separately and independently. This segmentation allows the decoding process to be broken into smaller, more manageable units that consume less power individually, while collectively providing the same error correction capability as processing all nodes together.
Solution Approach 2:
The patent implements early termination of the decoding process by checking whether decoding has succeeded before completing all iteration updates. When the syndrome becomes zero indicating successful decoding, the process stops immediately, avoiding unnecessary computations and reducing power consumption while maintaining data integrity.
2Reliability
If LDPC codes are used to improve data integrity, then error correction capability is improved, but computing resources increase
Solution Approach 1:
By segmenting variable nodes into groups and processing them separately, the patent reduces the computational burden on any single processing unit. Each group can be handled by dedicated hardware or software modules, distributing the computing resources required and reducing the peak demand on any single resource.
Solution Approach 2:
The patent performs preliminary checks after each group update to determine if decoding has succeeded. This preliminary action allows the system to avoid performing full iteration computations when decoding is already complete, thereby reducing the total computing resources required while ensuring data integrity.
3Reliability
If traditional BCH codes are used, then power consumption is lower, but error correction capability is insufficient for NAND flash devices
Solution Approach 1:
The patent implements partial processing by updating only one group of variable nodes per iteration rather than all nodes. This partial action reduces the computational workload and power consumption per iteration, allowing LDPC codes to achieve their superior error correction capability with lower overall power consumption compared to traditional BCH codes.
Solution Approach 2:
The patent employs periodic group updates where different groups of variable nodes are updated in successive iterations. This periodic approach distributes the computational load over time, reducing peak power consumption while maintaining the iterative refinement process necessary for LDPC error correction capability.
Data Source
AI summary
Decoding an LDPC encoded codeword is disclosed. Variable nodes corresponding to a parity check matrix of the LDPC encoded codeword have been divided into a plurality of groups. A selected group of variable nodes from the plurality of groups of variable nodes is updated. Check nodes are updated using a min-sum update. A selected input value provided from a variable node of the selected group of variable nodes and provided to a certain check node of the check nodes is discarded to be not available for use in a future min-sum update.