LDPC Decoder Scheduling for Lower-Latency Variable-Node Processing
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Solution Overview
Problem
Existing error correction coding (ECC) decoders, particularly for Low Density Parity Check (LDPC) codes, face inefficiencies in decoding latency and power consumption due to the need to process all variable nodes in each iteration, which can be wasteful and inefficient, especially for irregular codes where variables have different degrees.
Innovation Solution
A decoder system with logic circuitry that employs a scheduling scheme to selectively process or skip variable-node circuits based on predefined flipping thresholds and iteration-specific criteria, reducing the number of nodes processed in each iteration while ensuring decoding performance by focusing on unsatisfied check equations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all variable nodes are processed in each iteration, then decoding reliability is maintained, but decoding latency and power consumption increase
Solution Approach 1:
The patent applies partial action by processing only a subset of variable nodes in each iteration rather than all nodes. The scheduling scheme selectively identifies and processes only those variable nodes that are likely to contribute to error correction based on current syndrome status and node degrees, thereby reducing decoding latency while maintaining sufficient reliability through targeted processing of critical nodes
2Reliability
If all variable nodes are processed in each iteration, then decoding accuracy is maintained, but power consumption increases
Solution Approach 1:
The patent reduces power consumption by performing partial processing of variable nodes in each iteration. The scheduling mechanism identifies a subset of variable nodes that need processing based on their contribution to satisfying check equations, avoiding unnecessary computations on nodes that would not affect decoding accuracy, thereby reducing overall power consumption while maintaining decoding performance
3Ease of manufacture
If variable nodes with different degrees are processed uniformly, then implementation simplicity is maintained, but efficiency decreases for irregular codes
Solution Approach 1:
The patent applies local quality by treating variable nodes with different degrees differently in the scheduling process. The scheduling scheme considers the degree distribution of irregular LDPC codes and assigns processing priorities based on local node characteristics, such as processing high-degree nodes that are more critical for error correction first, thereby improving decoding efficiency for irregular codes while maintaining reasonable implementation complexity
Data Source
AI summary
A decoder includes multiple variable-node circuits and logic circuitry. The variable-node circuits hold variables of an Error Correction Code (ECC), defined by a set of check equations over multiple variables corresponding to the variable-node circuits. The logic circuitry is configured to receive a code word encoded using the ECC, to hold, prior to decoding in a sequence of iterations, a scheduling scheme that specifies, for each iteration, whether each of the variable-node circuits is to be processed or skipped in that iteration, to perform the iterations in the sequence, including selecting for processing, in each iteration, only variable-node circuits specified for processing in that iteration, to determine for each selected variable-node circuit, a count of unsatisfied check equations in which the respective variable participates, and to make a decision on flipping a binary value of the variable based on the count and apply the decision by the respective variable-node circuit.