LDPC Decoder Parallelism Switching for 5G Resource Constraints

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Solution Overview

Problem

Existing LDPC decoders face challenges with high hardware resource consumption and inflexibility due to excessive parallelism, which is not suitable for scenarios with limited resources and varying traffic demands in 5G mobile communication systems.

Innovation Solution

A decoding method and device that allows for variable parallelism, splitting and recombining soft information to optimize decoder performance, enabling flexible application and reduced resource consumption by adjusting parallelism based on specific scenarios and requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If high parallelism is used to meet decoding throughput requirements, then decoding performance is improved, but hardware resource consumption increases

Engineering Contradiction:
Improvedecoding throughputVSAvoidhardware resource consumption
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent implements dynamic parallelism adjustment by introducing a parallelism adjustment module that can change the parallelism degree of the decoder based on traffic conditions. The system switches between different parallelism modes (high parallelism for large traffic, low parallelism for small traffic) to optimize both throughput and resource consumption, making the parallelism level adaptive rather than fixed.

Inventive Principle:
Principle #15Dynamics

2Productivity

If high parallelism is configured to support maximum expansion factor, then decoding capability is improved, but flexibility for different scenarios is reduced

Engineering Contradiction:
Improvedecoding capabilityVSAvoidflexibility for different scenarios
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The system dynamically adjusts parallelism based on traffic conditions and code parameters. The parallelism adjustment module monitors traffic size and decoder workload, then switches between high and low parallelism modes appropriately. This dynamic adaptation enables the decoder to be flexible across different scenarios (smart terminal, IoT, base station) while maintaining high capability when needed.

Inventive Principle:
Principle #15Dynamics

3Productivity

If fixed high parallelism is used, then peak throughput is improved, but cost-performance ratio deteriorates

Engineering Contradiction:
Improvepeak throughputVSAvoidcost-performance ratio
Core Design Contradiction:
ProductivityVSEase of manufacture

Solution Approach 1:

The patent implements dynamic parallelism adjustment by introducing a parallelism adjustment module that can change the parallelism degree of the decoder based on traffic conditions. The system switches between different parallelism modes (high parallelism for large traffic, low parallelism for small traffic) to optimize both throughput and resource consumption, making the parallelism level adaptive rather than fixed.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the parallelism parameter dynamically based on traffic conditions. The parallelism adjustment module modifies operational parameters (parallelism degree) in response to changing conditions, transitioning between high and low parallelism states to optimize cost-performance ratio while maintaining adequate throughput for each scenario.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11483011B2Decoding method, decoding device, and decoder
Publication Date: 2022.10.25 ZTE CORP
  • US11483011B2 patent drawing
  • US11483011B2 patent drawing
  • US11483011B2 patent drawing

AI summary

Provided are a decoding method, a decoding device and a decoder. The method includes: setting a decoder parallelism P, and splitting soft information of a block to be decoded according to the parallelism P; performing decoding calculation on the block to be decoded according to the split information, and outputting decoded hard bit information; and recombining the hard bit information according to the parallelism P.