LDPC Bit-Flip Decoder Column Scheduling for Parity Separation

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Solution Overview

Problem

Conventional bit-flipping LDPC decoders face accuracy degradation due to concurrent processing of parity columns in pipeline and parallel processing, especially when there are high row overlaps between columns, leading to outdated syndrome states.

Innovation Solution

Reordering columns of the parity matrix to separate parity columns in pipeline processing, organizing them into Cycle Blocks and Pipeline Blocks, and assigning columns to processing units to avoid concurrent processing of multiple parity columns, ensuring each processing unit processes only one parity column at a time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If concurrent processing of parity columns is implemented in pipeline and parallel processing, then productivity is improved, but measurement precision deteriorates due to outdated syndrome states

Engineering Contradiction:

Improvedecoding throughputVSAvoiddecoding accuracy

Core Design Contradiction:

ProductivityVSMeasurement precision

Solution Approach 1:

The parity columns are segmented into different processing groups (first plurality and second plurality) that are processed at different times. The first parity columns are processed in an first iteration while the second parity columns are processed in a second iteration, preventing concurrent processing of multiple parity columns and avoiding outdated syndrome states.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The decoding process uses periodic iterations where parity columns are processed in alternating iterations. In one iteration, odd-indexed parity columns are processed; in the next iteration, even-indexed parity columns are processed. This periodic separation ensures that syndrome states remain current for each processing step.

Inventive Principle:

Principle #19Periodic action

2Productivity

If multiple parity columns are processed in parallel, then productivity is improved, but reliability deteriorates due to high row overlaps causing outdated syndrome states

Engineering Contradiction:

Improveprocessing speedVSAvoiddecoding reliability

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

Parity columns are segmented into disjoint sets that are processed in separate iterations. The first set contains parity columns at odd positions (1, 3, 5, ...) and the second set contains parity columns at even positions (2, 4, 6, ...). This segmentation eliminates row overlap conflicts between concurrently processed columns.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The problematic parity columns that cause row overlaps are extracted from the concurrent processing group and processed separately in alternating iterations. This extraction removes the source of reliability degradation while maintaining parallel processing benefits for non-overlapping columns.

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS12014071B2Separation of parity columns in bit-flip decoding of low-density parity-check codes with pipelining and column parallelism

Publication Date: 2024.06.18 MICRON TECHNOLOGY INC

AI summary

A memory device having a bit-flipping decoder. The decoder having a plurality of circuits operatable to perform parallel computation to decode a codeword according to a plurality of columns of a parity matrix. The decoder is configured to provide columns of the parity matrix for processing in the plurality of circuits in an order where columns processed concurrently by the plurality of circuits in pipeline stages include no more than one parity column of the parity matrix.