LDPC Decoder Partial Parallel Scheduling for Faster Convergence
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Solution Overview
Problem
The existing LDPC decoding methods in communication systems suffer from increased time delays due to the iterative nature of sum-product decoding algorithms, which affects the efficiency of high-speed data transmission.
Innovation Solution
The implementation of Partial Parallel Scheduling (PPS) in LDPC decoding, where offsets are set to determine the start position of node operations for each block column or row of the parity check matrix, allowing for parallel processing and reducing memory conflicts, thereby accelerating the decoding process without compromising performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If sequential bit node operation and check node operation are performed on all nodes in LDPC decoding, then decoding accuracy is maintained, but decoding time delay increases
Solution Approach 1:
The patent divides the parity check matrix into multiple block columns and processes them in parallel using multiple bit node updaters, each handling a specific block column. This segmentation enables simultaneous processing of different matrix blocks, reducing overall decoding time while maintaining accuracy through complete coverage of all nodes across iterations
Solution Approach 2:
The patent implements dynamic scheduling where the start position (offset) of bit node operations is adjusted for each block column based on the number of non-zero block matrices. This dynamic offset mechanism allows optimal parallel processing configuration that adapts to the specific structure of the LDPC code, enabling faster convergence without sacrificing decoding reliability
2Productivity
If parallel processing is implemented in LDPC decoding, then decoding speed increases, but memory conflicts occur between non-zero block matrices with the same shift parameters
Solution Approach 1:
The patent assigns different start positions (offsets) to different bit node updaters based on their assigned block columns. This local differentiation in operation timing prevents simultaneous access to the same memory locations by different updaters, eliminating memory conflicts while preserving the benefits of parallel processing for improving decoding speed
3Object-generated harmful factors
If offsets are set for each block column to enable parallel processing, then memory conflicts are prevented, but system complexity increases
Solution Approach 1:
The patent determines offsets based on the number of non-zero block matrices in each block column, transforming the structural properties of the parity check matrix into scheduling parameters. This parameter-based approach provides a systematic and automated method for setting offsets, reducing scheduling complexity while effectively preventing memory conflicts through mathematically determined timing adjustments
Data Source
AI summary
Provided are an apparatus and method for receiving a signal in a communication system, in which a signal is received and decoded by setting an offset indicating a start position of a node operation for each block column of a parity check matrix of a Low Density Parity Check (LDPC) code and scheduling an order of performing the node operation on a Partial Parallel Scheduling (PPS) group basis. Here, the parity check matrix includes p×L rows and q×L columns, the p×L rows are grouped into p block rows, the q×L columns are grouped into q block columns, and each PPS group includes one column from each of the q block columns.