Layered Multi-Level LDPC Decoder With Ping-Pong Memory

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Solution Overview

Problem

Multi-level LDPC codes offer better performance than binary LDPC codes but result in prohibitively large hardware size and power consumption due to increased complexity, limiting their practical application in real signal transmission systems.

Innovation Solution

A novel layered multi-level LDPC decoder architecture with a ping-pong memory and efficient processing units that reduce memory requirements and processing complexity, allowing for parallel processing while minimizing size and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multi-level LDPC codes are used to improve error correction performance, then decoding performance is improved, but hardware complexity increases leading to large size and power consumption

Engineering Contradiction:
Improveerror correction performanceVSAvoidhardware complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The multi-level LDPC decoder is divided into multiple binary LDPC decoders operating in parallel, each handling a specific level. The input soft values are segmented and distributed to appropriate decoders based on their significance, and the outputs are combined to produce the final decoded result. This segmentation allows the system to achieve multi-level decoding performance using simpler binary decoder building blocks.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Multiple binary LDPC decoders are merged into a unified multi-level decoding system through a combination network that integrates their outputs. The individual decoder results are combined according to the multi-level code structure to reconstruct the original transmitted data with enhanced error correction capability, achieving the performance of complex multi-level decoding through combination of simpler components.

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If multi-level LDPC codes are used to improve error correction performance, then decoding performance is improved, but hardware size becomes prohibitively large

Engineering Contradiction:
Improveerror correction performanceVSAvoidhardware size
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The decoder architecture segments the multi-level decoding task into multiple independent binary decoding operations. Each binary decoder processes a portion of the soft input values corresponding to a specific bit level, reducing the memory and computational requirements for each individual decoder unit. This segmentation enables the overall system to achieve multi-level performance with reduced per-unit hardware size.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The same binary LDPC decoder design is used universally across multiple levels, with each decoder instance performing the same function on different portions of the input data. This multi-functionality approach allows the system to reuse proven binary decoder architectures rather than designing entirely new complex multi-level decoders, thereby controlling hardware size while maintaining performance.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If multi-level LDPC codes are used to improve error correction performance, then decoding performance is improved, but power consumption becomes prohibitively high

Engineering Contradiction:
Improveerror correction performanceVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The power consumption burden is segmented across multiple independent binary decoder units, each consuming less power than a single equivalent multi-level decoder would require. By distributing the computational workload across multiple low-power binary units operating in parallel, the overall system achieves multi-level performance with controlled total power consumption.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Instead of implementing a complex multi-level decoder from scratch, the system creates multiple copies of a simpler, well-optimized binary LDPC decoder design. Each copy processes a specific level, and the collective output achieves multi-level decoding performance. This copying strategy leverages the lower power requirements of binary decoders while achieving the performance goals of multi-level codes.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS9037938B2Hardware architecture and implementation of low power layered multi-level LDPC decoder
Publication Date: 2015.05.19 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US9037938B2 patent drawing
  • US9037938B2 patent drawing
  • US9037938B2 patent drawing

AI summary

A layered LDPC decoder sorts and selects a subset of message entries for processing based on entry size. MIN1 and MIN2 values for each message entry in the subset are truncated, and either the truncated values or non-truncated values are combined with a symbol vector based on whether the subset of message entries includes a variable node associated with the layer being processed.