LDPC Decoder Layout With Single Permutation Network and Pipelined Layers
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Solution Overview
Problem
Traditional high-throughput LDPC decoders face challenges with high decoding complexity, excessive hardware resource consumption, and high power consumption due to their full-parallel decoding method, which also results in poor time sequence and reduced maximum clock frequency.
Innovation Solution
A layered semi-parallel LDPC decoder system with a single permutation network is introduced, utilizing the minimum-sum decoding algorithm and incorporating a pipeline design for layered semi-parallel decoding. This design reduces hardware resources by completing cyclic shift operations through a single permutation network and achieves nearly ¾ of the throughput of a full-parallel decoder.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If full-parallel decoding method is adopted to achieve high throughput, then decoding speed and throughput are improved, but decoding complexity increases exponentially and hardware resources are excessively consumed
Solution Approach 1:
The check nodes are divided into multiple groups, and decoding is performed in layers where each layer processes a subset of check nodes. This segmentation reduces the parallel decoding complexity from exponential to linear while maintaining high throughput through pipelined processing of multiple layers.
Solution Approach 2:
The decoding process is organized into periodic layers, where each layer completes processing of its assigned check nodes before transitioning to the next layer. This periodic structure enables pipelining and maintains steady throughput while controlling complexity through sequential layer processing.
2Productivity
If full-parallel decoding method is adopted to achieve high decoding rate, then throughput rate is improved, but hardware resources and power consumption increase significantly
Solution Approach 1:
By segmenting check nodes into groups and processing them in layers, the hardware resources required for parallel processing are reduced. Each layer uses a subset of the total hardware resources, enabling high throughput through time-multiplexed layer processing rather than requiring all resources simultaneously.
Solution Approach 2:
The decoding architecture transitions from a single-dimensional full-parallel approach to a multi-dimensional layered structure with pipelining. This adds temporal and structural dimensions to the processing, allowing high throughput to be achieved through coordinated layer progression rather than brute-force parallelism.
3Speed
If full-parallel decoding method is adopted, then decoding speed is improved, but circuit line block and long interconnection occur leading to poor time sequence and reduced maximum clock frequency
Solution Approach 1:
The circuit is segmented into layer-specific processing units with localized interconnections. Each layer processes its assigned check nodes with minimal long-distance signaling, reducing line block and improving time sequence. The maximum clock frequency is enhanced by eliminating the need for complex full-circuit interconnections.
Solution Approach 2:
The periodic layer-based processing creates a rhythmic flow of data through the circuit, improving time sequence coordination. Each layer activates in sequence, creating predictable timing patterns that reduce interconnection complexity and allow for higher clock frequencies with stable signal propagation.
Data Source
AI summary
The present invention relates to a layered semi-parallel LDPC decoder system having a single permutation network, and belongs to the field of decoder hardware design. The system comprises a layered decoding architecture of the single permutation network, a layered semi-parallel decoding architecture of the single permutation network, a pipeline design for layered semi-parallel decoding and a hardware framework of a layered semi-parallel LDPC decoder. The present invention removes a permutation network module between a check node and a variable node by modifying the cyclic shift value of each information block transferred from the variable node to the check node, i.e., the cyclic shift operation of the decoder can be completed through the single permutation network so as to reduce hardware resources of the decoder. A semi-parallel decoding structure is adopted, and meanwhile, a pipeline is added between half layers. Compared with a decoder with a layered full-parallel structure, a decoder with a semi-parallel structure has the degree of parallelism of a variable node equal to only half of the code length but can achieve ¾ of the throughput as well as reduce hardware resources by half.