LDPC Decoder Check-Node Scheduling for Lower Power Decoding
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Solution Overview
Problem
Existing ECC decoders face a tradeoff between error correction capability and power consumption, with higher error correction capability requiring more complex decoding processes and increased power consumption.
Innovation Solution
Implementing a method that determines a variable node to check node message and selects a check node processing mode based on message reliability, using different processing modes to optimize power consumption while maintaining error correction capability, by estimating reliability through syndrome-related parameters and switching between low and high complexity processing modes as needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If higher error correction capability is implemented through more complex decoding processing, then error correction performance is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic check node processing modes that adapt based on message reliability. The system switches between low complexity mode (for reliable messages) and high complexity mode (for unreliable messages), making the decoding process dynamic rather than static. This resolves the contradiction by using high power consumption only when necessary for error correction, rather than continuously
Solution Approach 2:
The patent changes the processing parameter (complexity level) based on the reliability parameter of incoming messages. When message reliability is high, the system uses low complexity processing; when reliability is low, it switches to high complexity processing. This parameter adaptation allows the system to maintain error correction capability while minimizing power consumption
2Reliability
If higher error correction capability is implemented through more complex decoding processing, then error correction performance is improved, but device complexity increases
Solution Approach 1:
The patent segments the check node processing into two distinct modes: low complexity mode and high complexity mode. This segmentation allows the system to apply different levels of processing complexity to different messages based on their reliability, rather than using a single uniform complex processing approach for all messages
Solution Approach 2:
The patent applies partial action by using high complexity processing only for the subset of messages that require it (those with low reliability), rather than applying full complexity processing to all messages. This partial application of complex processing maintains error correction capability while reducing overall device complexity
Data Source
AI summary
Techniques related to improving power consumption of an LDPC decoder are described. In an example, the LDPC decoder uses a message passing algorithm between variable nodes and check nodes. A check node processing unit that generates check node to variable node messages implements a plurality of check node processing mode. Operation in each mode consumes a certain amount of power while providing a certain accuracy. Depending on a reliability of a variable node to check node message received by the check node processing unit, an appropriate check node processing mode is selected and used to generate a corresponding check node to variable node message. The reliability can be estimated for a set of variable node to check node messages based on, for instance, syndrome-related parameters.