LDPC Decoder Architecture With Reduced Routing and Memory

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Low density parity check (LDPC) decoders face complexity in interconnect issues and high memory requirements due to complex message routing and storage, particularly in parallel implementations for randomly constructed LDPC codes.

Innovation Solution

The proposed solution involves a novel LDPC decoder architecture that includes a check node unit (CNU) with comparators for comparing stored minimum values to a received variable message, reducing message storage memory and routing logic complexity. This architecture features a set of comparators with fewer than the check node degree, allowing for efficient processing and message passing without active routers, and employs cyclic shift mechanisms to simplify interconnects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If parallel LDPC decoder architecture is used to improve decoding speed, then productivity is improved, but device complexity increases due to complex interconnect issues and message routing logic

Engineering Contradiction:

Improvedecoding speedVSAvoidinterconnect complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The decoder is divided into multiple independent check node unit arrays, where each array processes a specific block row of the LDPC parity check matrix. This segmentation allows parallel processing while reducing interconnect complexity within each array boundary.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Cyclic shift mechanisms are introduced as intermediaries to simplify message routing between variable nodes and check nodes. The cyclic shift buffers act as mediators that reduce the complexity of direct interconnect routing in parallel architectures.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Measurement precision

If more comparators are used in CNU to improve measurement precision, then measurement precision is improved, but device complexity increases

Engineering Contradiction:

Improveminimum value comparison precisionVSAvoidcomparator logic complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

Instead of using all check node degree comparators, the invention uses a reduced set of comparators that process only the necessary minimum values (M1 and M2). This partial action approach achieves sufficient precision for LDPC decoding while reducing device complexity.

Inventive Principle:

Principle #16Partial or excessive action

3Reliability

If message storage memory is increased to improve reliability, then reliability is improved, but device complexity increases due to message routing logic

Engineering Contradiction:

Improveerror correction reliabilityVSAvoidmessage routing logic

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The check node units perform self-service by maintaining their own minimum value storage and comparison logic locally. This eliminates the need for complex centralized message routing and storage, reducing device complexity while maintaining reliability through local error correction capabilities.

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS11728828B2Low density parity check decoder

Publication Date: 2023.08.15 TEXAS A&M UNIVERSITY

AI summary

A method and system for decoding low density parity check (“LDPC”) codes. An LDPC code decoder includes LDPC decoding circuitry comprising a Q message generator and a P sum adder array. The Q message generator combines an R message from a previous iteration with a P message to produce a Q message. The P sum adder array adds the P message to a difference of an R message from a current iteration and the R message from the previous iteration to produce an updated P message.