Adaptive LDPC Decoder Routing for NAND Flash Reliability

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Solution Overview

Problem

Current memory systems using NAND flash devices face challenges in data reliability due to increased noise and interference, requiring more powerful error correction codes, and existing decoding algorithms struggle to accurately predict decoding failures, leading to inefficiencies and higher power consumption.

Innovation Solution

A memory system that includes a controller configured to determine a quality metric based on initial syndrome weight and information from a bit-flipping decoder after a set number of iterations, deciding whether to send codewords to a bit-flipping decoder or a min-sum decoder for decoding, optimizing the decoding process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If more powerful error correction codes (such as LDPC) are used to overcome noise and interference, then data reliability is improved, but decoding complexity and power consumption increase

Engineering Contradiction:
Improvedata reliabilityVSAvoiddecoding complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system dynamically selects between different decoding algorithms (BF or MS) based on the characteristics of each codeword being decoded. The controller evaluates codeword properties and adaptively chooses the most appropriate decoding method, transitioning from static to dynamic operation to balance reliability and complexity

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the decoding parameter (algorithm type) based on codeword characteristics. By monitoring codeword properties and adjusting the decoding approach accordingly, the system optimizes the balance between error correction capability and computational complexity

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If multiple decoding algorithms are used to decode different codewords based on conditions, then decoding accuracy is improved, but system complexity increases

Engineering Contradiction:
Improvedecoding accuracyVSAvoidsystem complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

Different decoding algorithms are applied to different codewords based on their individual characteristics. Each codeword receives the decoding treatment most suitable for its specific properties, rather than applying a uniform approach to all codewords

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The system dynamically selects between different decoding algorithms (BF or MS) based on the characteristics of each codeword being decoded. The controller evaluates codeword properties and adaptively chooses the most appropriate decoding method, transitioning from static to dynamic operation to balance reliability and complexity

Inventive Principle:
Principle #15Dynamics

3Reliability

If powerful decoders are used for all codewords, then data integrity is improved, but power consumption increases

Engineering Contradiction:
Improvedata integrityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The system applies the more powerful minimum-sum decoding algorithm only partially - specifically to codewords that require it based on their characteristics. For codewords that can be successfully decoded by the simpler bit-flipping algorithm, the excessive action of using MS decoding is avoided, thus reducing overall power consumption while maintaining data integrity

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS10700706B2Memory system with decoders and method of operating such memory system and decoders
Publication Date: 2020.06.30 SK HYNIX INC
  • US10700706B2 patent drawing
  • US10700706B2 patent drawing
  • US10700706B2 patent drawing

AI summary

A memory system, a controller including a bit-flipping (BF) decoder and a min-sum (MS) decoder that may be included in the memory system and operating methods thereof in which the controller determines a quality metric as a function of initial syndrome weight and information of the BF decoder after a set number of decoding iterations by the BF decoder in a test period. After the test period, the controller applies the quality metric to each codeword to determine whether to send that codeword first to the BF decoder for decoding or directly to the MS decoder for decoding.