Frame-Interleaved LDPC Decoder Layout for Routing-Efficient Throughput
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Solution Overview
Problem
Conventional LDPC decoder architectures face challenges in achieving multi-Gb/s throughput due to complex interconnects and routing logic, especially in bandwidth-limited systems, and struggle with error correction performance and scalability, particularly in next-generation CMOS technology nodes.
Innovation Solution
A frame-interleaved LDPC decoder architecture that exploits the cyclic structure of LDPC parity-check matrices through a new interconnect partitioning scheme and time-distributed Min-Sum decoding schedule, reducing routing congestion and energy efficiency by combining CN-phase and VN-phase update logic into a single processing unit with deterministic memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional LDPC decoder architectures are used, then error correction performance can be maintained, but interconnect complexity and routing logic become excessive
Solution Approach 1:
The decoder is segmented into column slice circuits that are organized in a pipeline arrangement, with each slice processing specific columns of the parity-check matrix. This segmentation reduces interconnect complexity by localizing routing within each slice while maintaining error correction performance through systematic message passing between slices.
Solution Approach 2:
The architecture transitions from a two-dimensional array structure to a three-dimensional pipeline arrangement of column slice circuits. This dimensional change enables time-distributed processing where messages flow through multiple pipeline stages, reducing spatial interconnect complexity while preserving decoding functionality.
2Speed
If multi-Gb/s throughput is achieved, then data processing speed increases, but interconnect complexity and routing logic increase
Solution Approach 1:
The decoder employs a dynamic pipeline architecture where column slice circuits can be selectively activated and deactivated based on the desired code rate and throughput requirements. This dynamic configuration allows the system to achieve multi-Gb/s throughput by enabling more pipeline stages while maintaining manageable routing logic through systematic activation patterns.
Solution Approach 2:
The pipeline architecture implements periodic processing where each column slice circuit operates in regular cycles, processing messages at fixed intervals. This periodic action enables predictable throughput scaling to multi-Gb/s rates while keeping routing logic systematic and manageable through regular timing patterns.
3Device complexity
If CN-phase and VN-phase update logic are combined into a single processing unit, then device area and interconnect complexity are reduced, but processing speed may be affected
Solution Approach 1:
Check node update logic and variable node update logic are merged into unified column processing nodes within each column slice circuit. This merging reduces the number of separate processing units and interconnects, simplifying the overall architecture while maintaining processing speed through careful timing and pipeline staging of the combined operations.
Solution Approach 2:
The pipeline architecture ensures continuous processing by overlapping the execution of CN-phase and VN-phase updates across different pipeline stages. While one phase is being computed in a given stage, another phase is simultaneously processed in adjacent stages, maintaining continuous useful action and preserving overall processing speed despite the merged structure.
Data Source
AI summary
A Low-Density Parity-Check (LDPC) decoder and a method for LDPC decoding are provided. The LDPC decoder receives a soft-decision input codeword block in which the probability of a bit being a “0” or a “1” is represented as a log-likelihood ratio (LLR). During LDPC decoding, a sequence of hardware logic units iteratively updates the soft-decision input codeword block until a valid codeword is found or a maximum number of decoding iterations is reached. Each hardware logic unit comprises a check node (CN) update logic unit and a variable node (VN) update logic unit. The CN update logic units are coupled via a closed CN path, and the VN update logic units are coupled via a closed VN path. Aspects of this LDPC decoder alleviate the global routing and energy efficiency challenges of traditional LDPC decoders, to enable multi-rate, multi-Gb/s decoding without compromising error correction performance in next-generation systems and future CMOS technology nodes.