LDPC Decoder Scheduling to Reduce Row Processing Stalls
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Solution Overview
Problem
The increasing data volume in 5G communication systems necessitates faster decoding of Low Density Parity Check (LDPC) codes to manage errors effectively.
Innovation Solution
A decoding apparatus that utilizes a scheduling table to determine the processing order of rows and columns in the parity check matrix, allowing for the processing of columns in a second row before all columns in a first row are completed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If sequential row-by-row processing is used in LDPC decoding, then processing order is simple and easy to implement, but decoding speed is slow due to stalls
Solution Approach 1:
The patent pre-calculates and stores an optimal processing order in a scheduling table before decoding begins. This scheduling table indicates the desired processing order of rows and columns in the parity check matrix, allowing the decoder to avoid stalls by processing columns in an optimized sequence rather than simple row-by-row order.
Solution Approach 2:
The patent introduces dynamic processing by allowing the decoder to switch between different processing orders (row-by-row vs. scheduled order) and to independently process columns from different rows based on the scheduling table, rather than being constrained to a fixed sequential approach.
2Productivity
If all columns in the first row are processed before moving to the second row, then processing is systematic and organized, but stalls occur that reduce decoding efficiency
Solution Approach 1:
The scheduling table is pre-computed to identify and eliminate stall conditions before decoding begins. The table stores the optimal processing sequence that prevents stalls by indicating which columns should be processed from subsequent rows before all columns in the current row are completed.
Solution Approach 2:
The patent eliminates idle stall periods by continuously processing columns in an optimized order. The scheduling table ensures that processing continues without interruption by allowing the decoder to switch between rows smoothly, maintaining continuous useful action throughout the decoding process.
Data Source
AI summary
There is provided a decoding apparatus for decoding a low density parity check (LDPC) code, wherein the decoding apparatus includes a memory a memory configured to store a scheduling table indicating a desired processing order of a plurality of rows included in a parity check matrix and a plurality of columns included in each of the rows of the parity check matrix, and processing circuitry configured to decode the LDPC code based on the scheduling table, the decoding including performing processing on at least one column included in a second scheduled row of the parity check matrix before processing of all columns included in a first scheduled row of the parity check matrix has been completed.