LDPC Decoder Pre-Saturation Compensation for Error Floor Reduction

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Solution Overview

Problem

Min-sum LDPC decoders face challenges in the error floor region due to message saturation, which hinders the differentiation of large channel LLR values and leads to increased bit error rates, especially in low noise conditions where trapping sets resist easy resolution.

Innovation Solution

The implementation of a pre-saturation compensation circuit that scales or biases v2c messages to prevent saturation, using scaling factors, biasing factors, or LLR look-up tables to maintain message magnitudes below the maximum available, thereby facilitating error resolution in both the waterfall and error floor regions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If message magnitude is increased to differentiate large channel LLR values, then measurement precision is improved, but saturation occurs at the maximum value that can be expressed using p bits

Engineering Contradiction:
Improvedifferentiation of channel LLR valuesVSAvoidmessage saturation
Core Design Contradiction:
Measurement precisionVSObject-affected harmful factors

Solution Approach 1:

The patent applies preliminary anti-action by introducing a pre-saturation compensation circuit that proactively scales down v2c messages before they reach the check node circuit. This prevents saturation from occurring in the first place, allowing the system to maintain both high measurement precision for large LLR values and avoid the harmful saturation effect. The scaling operation is performed in advance based on the magnitude of incoming messages.

Inventive Principle:
Principle #9Preliminary anti-action

Solution Approach 2:

The patent changes the parameter of message magnitude dynamically through the pre-saturation compensation circuit. When large channel LLR values are detected, the circuit applies appropriate scaling factors to adjust the message magnitude, transforming it to fit within the p-bit representation capacity while preserving the relative differences needed for accurate differentiation.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If scaling or biasing operations are applied to prevent saturation, then reliability is improved, but device complexity increases

Engineering Contradiction:
Improveerror floor performanceVSAvoidadditional compensation circuit
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces an intermediary pre-saturation compensation circuit between the variable node circuit and check node circuit. This intermediary component performs the scaling or biasing operations on v2c messages, acting as a mediator that protects the check node circuit from saturation while maintaining overall system reliability. The intermediary approach isolates the complexity to a dedicated component rather than distributing it throughout the entire decoder.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If pre-saturation compensation is implemented, then throughput is improved in error floor region, but manufacturing precision requirements increase

Engineering Contradiction:
Improvedecoding throughputVSAvoidscaling factor accuracy
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent applies partial action by implementing pre-saturation compensation only when and where it is most needed - specifically for v2c messages that are at risk of saturating at the check node circuit. Rather than applying uniform processing to all messages, the compensation is selectively applied based on message magnitude, improving throughput in the error floor region while minimizing the impact on manufacturing precision requirements.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS10263640B2Low density parity check (LDPC) decoder with pre-saturation compensation
Publication Date: 2019.04.16 SEAGATE TECH LLC
  • US10263640B2 patent drawing
  • US10263640B2 patent drawing
  • US10263640B2 patent drawing

AI summary

Method and apparatus for decoding data. In some embodiments, an LDPC decoder has a variable node circuit (VNC) with a plurality of variable nodes configured to store bit reliability values of m-bit code bits. A check node circuit (CNC) has a plurality of check nodes configured to perform parity check operations upon n-bit messages from the VNC. Each n-bit message is formed from a combination of the bit reliability values and stored messages from the check nodes. A pre-saturation compensation circuit is configured to maintain a magnitude of each n-bit message received by the CNC below a saturation limit comprising the maximum value that can be expressed using p bits, with p less than n and each of the n-bit messages received by the CNC having a different magnitude. The pre-saturation compensation circuit may apply different scaling and/or bias factors to the n-bit messages over different decoding iterations.