Hard-Decision LDPC Decoder With Shared Logic for Low-Latency Decoding

The patent inverts the conventional processing order by processing bit values in the same order they are received, eliminating the need for reordering memory operations. This is achieved through a systematic reorganization of the parity check matrix processing to accommodate sequential bit input without requiring additional bit memory storage and retrieval operations.

The patent extracts and eliminates the bit memory component from the decoder architecture by redesigning the processing flow to work directly with incoming bit sequences. The syndrome calculator and bit-flipping logic are reconfigured to operate on sequential bit inputs without requiring intermediate storage, thereby removing the latency and area overhead associated with bit memory.

The patent implements multi-functionality by designing logic elements that serve dual purposes: the syndrome calculator performs both initial syndrome computation and ongoing syndrome updates during bit-flipping iterations. The same XOR gates and logic circuits are reused for different stages of decoding, eliminating redundant logic and reducing overall chip area while managing complexity through unified design.

The patent merges the bit-flipping decoder logic and syndrome calculator into a unified processing structure where shared logic elements perform both functions. The bit-flipping unit and syndrome computation unit are integrated such that they share common computational resources, reducing the total number of logic elements required while maintaining the functional separation needed for correct operation.