LDPC Decoder Shared-Memory Architecture for Reduced Storage
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Solution Overview
Problem
The existing LDPC decoding methods require significant memory storage and hardware resources due to the need for iterative data passing and customized check node codeword estimates between check nodes and variable nodes, leading to high memory storage requirements and complex logic routing.
Innovation Solution
A method that combines check node and variable node processing into a single processor with shared memory, eliminating the need for customized check node codeword estimates and reducing the number of common processing variables stored, thereby reducing memory storage requirements and hardware complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate check node processor and variable node processor are used with customized check node codeword estimates, then decoding accuracy is improved, but memory storage requirements and hardware complexity increase
Solution Approach 1:
The patent combines the check node processor and variable node processor into a single integrated processor unit. This merging eliminates the need for separate processing units and their associated interfaces, thereby reducing hardware complexity while maintaining the functional capabilities needed for accurate LDPC decoding through unified processing logic and shared memory resources.
Solution Approach 2:
The integrated processor is designed to perform both check node processing and variable node processing functions within a single unit. This multi-functional design allows the same hardware resource to execute different decoding operations sequentially, reducing overall hardware complexity while preserving decoding accuracy through proper implementation of both processing algorithms.
2Reliability
If separate check node processor and variable node processor are used with customized check node codeword estimates, then decoding performance is improved, but memory storage requirements increase
Solution Approach 1:
By merging the check node processor and variable node processor into a single integrated unit with shared memory, the patent eliminates redundant memory storage required for separate processing units. The shared memory architecture allows both processing functions to access common data structures, significantly reducing the total memory storage requirements while maintaining decoding performance through efficient data sharing.
Solution Approach 2:
The patent extracts the customization of check node codeword estimates from the check node processor and implements it within the variable node processor. This extraction eliminates the need for separate customized check node estimates, reducing memory storage requirements by removing redundant data structures while preserving decoding performance through the reformulated processing approach.
3Measurement precision
If iterative data passing between check nodes and variable nodes is implemented, then decoding accuracy is improved, but the amount of data to be stored and routed increases
Solution Approach 1:
The integrated processor merges the iterative data passing operations into a unified processing flow where check node and variable node processing are performed sequentially within the same hardware unit. This eliminates the need for extensive data routing between separate processors, reducing the volume of data that needs to be stored and transmitted while maintaining decoding accuracy through the iterative algorithm.
Data Source
AI summary
A low-density parity check (LDPC) decoder is provided that eliminates the need to calculate customized check node codeword estimates by considering the check node processor and the variable node processor as a single processer having a shared memory for storing common variables to be used during both the check node processing and the variable node processing of the iterative decoding method.