LDPC Decoder Shift-Register Architecture for Lower Memory Complexity
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Solution Overview
Problem
Low-density parity-check (LDPC) decoding is computationally complex, leading to increased memory requirements and interconnection complexity, which hinders efficient processing in systems like 60 GHz millimeter wave systems.
Innovation Solution
An iterative LDPC decoding system with a shift-register means for storing bit estimates, a parity-check processing means for generating messages, a combining means for updating bit estimates, and a fixed permutation means for facilitating storage and access, along with a second shift-register means for storing messages and subtracting earlier messages from updated bit estimates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If iterative LDPC decoding procedures are employed to improve decoding accuracy, then decoding reliability is improved, but computational complexity increases
Solution Approach 1:
The parity-check matrix H is divided into multiple sub-matrices, and the decoding process is segmented into multiple stages where each stage processes a subset of check nodes. This segmentation reduces the computational burden of each individual iteration while maintaining the iterative decoding structure needed for reliability.
Solution Approach 2:
The decoding process employs periodic cycling through different sub-matrices and check node sets. By periodically rotating through different segments of the parity-check matrix, the system distributes computational load across multiple cycles, reducing peak complexity while maintaining convergence properties.
2Device complexity
If computational complexity is reduced to simplify processing, then device complexity is reduced, but memory requirements increase
Solution Approach 1:
Multiple shift registers are nested within the decoding architecture, with each register storing intermediate results from different processing stages. This nesting allows efficient reuse of stored data across iterations without requiring separate memory allocations, reducing overall memory requirements while maintaining reduced computational complexity.
3Productivity
If iterative decoding procedures are implemented to improve decoding performance, then productivity is improved, but interconnection complexity increases
Solution Approach 1:
The interconnection structure is segmented into modular units corresponding to different sub-matrices and check node groups. Each module handles specific connections, reducing the complexity of any single interconnection path while maintaining the overall iterative decoding performance through coordinated operation of multiple segments.
Data Source
AI summary
An iterative low-density parity-check (LDPC) decoding system comprises a first shift register for storing bit estimates, a plurality of parity-check processing node banks configured for processing the bit estimates for generating messages, combiners configured for combining the messages with the bit estimates for generating updated bit estimates, and fixed permuters for permuting the updated bit estimates to facilitate storage and access of the bit estimates. A second shift register is provided for storing the messages, and a subtraction module subtracts messages generated a predetermined number of cycles earlier from the updated bit estimates.