LDPC Decoder Early Termination Using Parity and Sign Flip Bits

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Solution Overview

Problem

Current wireless communication systems face challenges in efficiently decoding low-density parity-check (LDPC) codes, particularly in determining when to terminate the decoding process to ensure accurate data recovery and reduce processing delays, which affects the performance and efficiency of LDPC decoders in high-speed applications.

Innovation Solution

The method involves maintaining an overall parity bit and a sign flip bit during the LDPC decoding process, where decoding is terminated only when both bits are true at the end of an iteration, ensuring that no sign flips have occurred and all parity checks are satisfied, thereby confirming the validity of the decoding results.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If LDPC decoding is terminated early to reduce processing delays, then the speed of decoding is improved, but the accuracy of decoded data may deteriorate

Engineering Contradiction:
Improveprocessing delaysVSAvoidaccuracy of decoded data
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The patent implements a feedback mechanism using sign flip bits that monitor decoding convergence in real-time. During iterative decoding, sign flip bits track whether log-likelihood ratio signs have stabilized across iterations. When sign flips cease and the overall parity bit confirms valid decoding, the system feedbacks a termination signal, allowing early exit while guaranteeing accuracy. This feedback loop resolves the contradiction by providing a reliable stopping criterion that prevents premature termination.

Inventive Principle:
Principle #23Feedback

2Reliability

If iterative decoding continues for more iterations to ensure accuracy, then the reliability of decoded data is improved, but the processing time increases

Engineering Contradiction:
Improveaccuracy of decoded dataVSAvoidprocessing delays
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent prepares termination criteria in advance by initializing sign flip bits and overall parity bits before decoding begins. The sign flip bits are pre-configured to monitor specific log-likelihood ratio positions, and the overall parity bit is pre-set to validate decoding completion. This preliminary setup enables rapid termination decision-making during iteration, allowing the system to exit early when criteria are met without requiring extensive additional iterations, thus reducing processing time while maintaining accuracy.

Inventive Principle:
Principle #10Preliminary action

3Ease of operation

If simple termination criteria are used to reduce complexity, then the ease of operation is improved, but the reliability of decoding termination may deteriorate

Engineering Contradiction:
Improvesimplicity of termination criteriaVSAvoidaccuracy of termination decision
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent introduces sign flip bits as intermediary indicators that mediate between complex decoding states and simple termination decisions. Instead of directly evaluating complex decoding convergence conditions, the system uses sign flip bits to track stabilization of log-likelihood ratios. This intermediary mechanism transforms a complex reliability assessment into a simple bit-check operation, maintaining high reliability while achieving ease of operation through straightforward termination criteria evaluation.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10312937B2Early termination technique for LDPC decoder architecture
Publication Date: 2019.06.04 QUALCOMM INC
  • US10312937B2 patent drawing
  • US10312937B2 patent drawing
  • US10312937B2 patent drawing

AI summary

Certain aspects of the present disclosure generally relate to methods and apparatus for decoding low density parity check (LDPC) codes, and more particularly to early termination techniques for low-density parity-check (LDPC) decoder architecture.