LDPC Decoder Memory Layout Using Single-Port RAMs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
LDPC decoders face challenges in rapidity of decoding algorithm completion and high power consumption due to the limitations of dual-port memories, particularly in large-scale LDPC decoding applications.
Innovation Solution
The use of single-port random access memories (SPRAMs) replaces dual-port memories, allowing for simultaneous read and write operations across two separate single-port memories, reducing the surface area and power consumption while maintaining efficient data processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If dual-port memories are used to enable simultaneous read and write operations, then decoding speed is improved, but surface area and power consumption increase
Solution Approach 1:
The patent divides the dual-port memory into two separate single-port memories. Each single-port memory handles either read or write operations, eliminating the need for dual-port memory while maintaining simultaneous read-write capability. This segmentation reduces the surface area required for memory implementation.
Solution Approach 2:
The patent introduces an intermediary mechanism (control logic and buffering) that coordinates between two single-port memories to achieve simultaneous read and write operations. This intermediary approach allows the system to function as if it had dual-port memory while using only single-port memories, reducing area consumption.
2Speed
If dual-port memories are used to enable simultaneous read and write operations, then decoding speed is improved, but power consumption increases
Solution Approach 1:
By segmenting the memory system into two separate single-port memories, each memory operates independently with lower power consumption. The total power consumption of two single-port memories is less than that of a dual-port memory providing the same functionality.
Solution Approach 2:
The patent uses simpler, less expensive single-port memories instead of more complex dual-port memories. While single-port memories have limitations, the system architecture compensates for this, achieving the desired performance with lower-cost, lower-power components.
3Productivity
If the number of processing units is increased to improve decoding throughput, then productivity is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent merges the functionality of multiple processing units into a more integrated architecture. By combining control logic, addressing mechanisms, and data flow management into a unified system, the decoder achieves high throughput without proportionally increasing complexity.
Solution Approach 2:
The processing units are designed with multi-functional capabilities, allowing each unit to perform multiple operations (read, write, process different data types) rather than requiring dedicated specialized units for each function. This universality reduces the total number of components needed.
Data Source
AI summary
An LDPC decoder having a determined number of processing units operating in parallel, storage circuitry capable of containing first words containing a juxtaposition of messages of a first type, and second words containing a juxtaposition of messages of a second type, a message provision unit capable of providing each processing unit with a message of the first type or a message of the second type, and a message write unit capable of writing, into the storage circuitry, first words or second words. The message provision unit is capable of providing a message at a position in a word which depends on the word or the message write unit is capable of writing each message at a position in the word which depends on the word.