LDPC Decoder Shift-Register Architecture With Single-RAM Data Handling

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Solution Overview

Problem

Conventional decoding devices for quasi cyclic low density parity check codes require a large number of random access memories (RAMs) to store and update intermediate data, leading to increased storage capacity and processing delays, especially in high coding rate scenarios where the Hamming weight of row vectors is high.

Innovation Solution

A decoding device using feedback shift register type check node processing devices with interconnected registers and comparator circuits, reducing the need for multiple RAMs by using a single memory and feedback shift registers to process and update data, while maintaining processing speed and reducing circuit size.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a larger number of RAMs are used to store intermediate data for high-speed decoding processing, then processing speed is improved, but storage capacity and device complexity increase

Engineering Contradiction:

Improvedecoding processing speedVSAvoidnumber of RAMs and storage capacity

Core Design Contradiction:

ProductivityVSQuantity of substance

Solution Approach 1:

The patent combines multiple RAMs into a single RAM by implementing data segmentation and time-division multiplexing. Intermediate data are divided into multiple segments that are sequentially read from and written to the single RAM, eliminating the need for multiple separate memory devices while maintaining the required data storage capacity and access patterns for decoding operations

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent segments intermediate data into multiple parts that can be processed and stored in a single RAM through time-division multiplexing. This segmentation allows the system to manage large amounts of intermediate data in a single memory device by organizing data access in sequential time slots, thereby reducing the total number of RAM devices needed

Inventive Principle:

Principle #1Segmentation

2Speed

If intermediate data are segmented and stored in multiple RAMs, then data access efficiency is improved, but device complexity and circuit size increase

Engineering Contradiction:

Improvedata access efficiencyVSAvoidcircuit size and number of components

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The patent implements dynamic data segmentation and time-division multiplexing control that adapts to different decoding stages and data access patterns. The system dynamically manages data segments within a single RAM, using control logic that adjusts data access sequences based on the decoding process requirements, thereby maintaining high data access efficiency without the static complexity of multiple fixed RAM devices

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The single RAM device is designed to perform multiple functions that would traditionally require separate specialized memory devices. It handles both intermediate data storage and temporary result storage, supports various data access patterns through time-division multiplexing, and adapts to different decoding operations, thereby replacing multiple specialized RAMs with one universal memory device

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS8667376B2Decoding device, data communication apparatus having the decoder device, and data memory

Publication Date: 2014.03.04 NEC CORP

AI summary

A decoding device comprises two check node processing devices of feedback shift register type, each of which node processing includes a plurality of registers and a plurality of comparator circuits. A multiplexer and a demultiplexer switch between the two check node processing devices, and a memory holds the two sorts of data. The comparator circuits are interposed between registers of the check node processing device.