LDPC Decoder Speed Control Using Unsatisfied Check Nodes
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Solution Overview
Problem
As the size of codewords increases, the time required for error correction decoding using low-density parity check (LDPC) codes also increases, leading to slower data output in memory systems due to complex calculations, which affects the operating speed of error correction operations.
Innovation Solution
An error correction decoder that performs iterative decoding operations, adjusts calculation speed based on the number of iterations and unsatisfied check nodes, using a speed selector to control the decoding speed dynamically, thereby optimizing the decoding process for subsequent codewords.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If iterative decoding operation is performed using LDPC code, then error correction reliability is improved, but decoding time increases
Solution Approach 1:
The patent applies dynamics by making the decoding speed variable rather than fixed. The speed selector dynamically adjusts the decoding speed based on real-time feedback from the syndrome generator about the number of unsatisfied check nodes. When error conditions are detected, the system slows down decoding to ensure accuracy; when no errors are present, it maintains higher speed, thus adapting the decoding process to actual channel conditions.
Solution Approach 2:
The patent implements feedback by using the syndrome generation result (number of unsatisfied check nodes) to control the decoding speed. The syndrome generator continuously monitors the decoding process and feeds this information back to the speed selector, which then adjusts the operational speed. This closed-loop feedback mechanism ensures that decoding reliability is maintained while optimizing speed based on actual error conditions.
2Productivity
If decoding speed is increased for subsequent codewords, then productivity is improved, but error correction reliability may deteriorate
Solution Approach 1:
The system dynamically adjusts decoding speed based on the syndrome results of previous codewords. The speed selector changes the operational speed for subsequent codewords according to the error conditions detected in prior decoding operations. This dynamic speed adjustment allows the system to optimize throughput when channel conditions are good while maintaining reliability when errors are detected.
Solution Approach 2:
The patent changes the operational parameter (decoding speed) based on the syndrome results. The speed selector modifies the speed parameter for subsequent decoding operations according to the number of unsatisfied check nodes observed in previous codewords. This parameter adaptation enables the system to balance productivity and reliability by adjusting speed according to actual channel quality.
3Productivity
If high speed decoding is used when error bits are high, then productivity is improved, but manufacturing precision of error correction deteriorates
Solution Approach 1:
The syndrome generator provides continuous feedback about the number of unsatisfied check nodes, which serves as an indicator of error severity. The speed selector uses this feedback to determine the appropriate decoding speed, slowing down when high error rates are detected and maintaining higher speed when errors are minimal. This feedback-driven speed control ensures that correction precision is maintained even when productivity needs to be optimized.
Solution Approach 2:
The system changes the decoding speed parameter based on the observed error conditions. When the syndrome indicates a high number of unsatisfied check nodes (suggesting many error bits), the system reduces speed to maintain correction precision. When error rates are low, the system increases speed to improve productivity. This adaptive parameter adjustment resolves the contradiction between speed and precision.
Data Source
AI summary
Provided herein may be an error correction decoder, an error correction circuit having the error correction decoder, and a method of operating the error correction decoder. The error correction decoder may include a calculator configured to output an error correction message by performing an iterative decoding operation on a first codeword, a syndrome generator configured to generate a syndrome by calculating the error correction message and a parity check matrix and to output a number of iterations representing the number of times the iterative decoding operation has been performed, and an unsatisfied check node (UCN) value representing the number of unsatisfied check nodes in the syndrome, and a speed selector configured to output a speed code for controlling a speed of the iterative decoding operation depending on the number of iterations and the UCN value.