LDPC Decoder Architecture With Split BNP for Lower Memory Access
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing LDPC decoder architectures require significant memory and processing resources due to complex iterative decoding processes, leading to high latency and inefficiency in satellite communications.
Innovation Solution
A novel LDPC decoder architecture is introduced, which separates bit node processing (BNP) into a BNP accumulator and a BNP extrinsic information calculator, reducing read and write operations to edge memory by splitting processing modules and optimizing extrinsic information handling between BNP and check node processing (CNP) iterations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a conventional LDPC decoder architecture is used, then decoding functionality is provided, but memory access complexity and processing latency are high
Solution Approach 1:
The bit node processing (BNP) is divided into two separate modules: a BNP accumulation module that performs summation operations, and a BNP extrinsic information calculator that computes extrinsic information. This segmentation reduces the number of read and write operations to edge memory, thereby reducing memory access complexity and processing latency.
2Reliability
If iterative decoding is implemented, then error correction capability is improved, but memory and processing resources are significantly increased
Solution Approach 1:
The decoder is segmented into specialized modules (BNP accumulation module, BNP extrinsic information calculator, CNP processor module) that perform specific functions iteratively. This segmentation allows the iterative decoding process to maintain error correction capability while reducing the overall memory and processing resource requirements through optimized data flow and reduced redundant operations.
Solution Approach 2:
Edge memory serves as an intermediary structure that stores accumulated values and extrinsic information between BNP and CNP iterations. This intermediary approach optimizes data exchange between processing modules, reducing the need for repeated memory accesses and lowering overall resource requirements while maintaining iterative decoding functionality.
3Manufacturing precision
If more read and write operations to edge memory are performed, then processing completeness is ensured, but processing latency increases
Solution Approach 1:
By segmenting BNP into accumulation and extrinsic information calculation modules, the patent reduces the frequency of memory operations while ensuring all necessary processing steps are completed. The BNP accumulation module writes to edge memory less frequently than conventional architectures, maintaining processing completeness while reducing latency.
Solution Approach 2:
The architecture enables continuous processing by keeping data in intermediate registers and buffers between operations, reducing the need for repeated memory reads and writes. This maintains processing completeness while minimizing memory access latency.
Data Source
AI summary
Systems, devices, and methods are disclosed for a novel LDPC decoder. An architecture is described to implement a novel sequence of bit node processing (BNP) and check node processing (CNP) operations. More specifically, the BNP may be split into two parts: a BNP accumulator and a BNP extrinsic information calculator. This separation of processing modules may provide for fewer read and write operations to and from edge memory.