LDPC Decoder Staging for Lower-Resource NAND Flash Decoding
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Solution Overview
Problem
Flash memory devices, particularly NAND flash devices, face challenges in reducing computation resource consumption during data reading, which affects overall performance due to their serial access nature and the need for efficient decoding of Low-Density Parity-Check (LDPC) codes.
Innovation Solution
A method and apparatus for decoding LDPC codes using a three-stage process involving variable-node and check-node calculation circuitries, with modulo 2 multiplication and bit flipping algorithms, to efficiently correct errors and reduce computation resources by utilizing Static Random Access Memory (SRAM) for storing codewords and soft bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional LDPC decoding process is used in NAND flash devices, then decoding capability is provided, but computation resource consumption is high
Solution Approach 1:
The decoding process is segmented into three distinct stages: first-stage decoding using only check-node calculation circuitry, second-stage decoding introducing variable-node calculation circuitry, and third-stage iterative decoding. This segmentation allows the system to use minimal computation resources for error-free codewords while escalating resource usage only when necessary, thereby resolving the contradiction between decoding capability and computation resource consumption.
Solution Approach 2:
The first-stage decoding performs preliminary error detection and correction using check-node calculation before proceeding to more resource-intensive variable-node calculation. This preliminary action filters out many cases that don't require full decoding, reducing overall computation resource consumption while maintaining decoding capability.
2Reliability
If a conventional LDPC decoding process is used in NAND flash devices, then decoding capability is provided, but overall performance is affected
Solution Approach 1:
The three-stage decoding process segments computation tasks to match error patterns, using simple check-node calculation for common cases and more complex variable-node calculation only when necessary. This segmentation improves overall performance by reducing average decoding time and computation resource consumption while maintaining high decoding capability.
Solution Approach 2:
The system performs partial decoding in the first stage using only check-node calculation, which handles many error patterns without requiring full variable-node processing. This partial action improves productivity by completing decoding faster for common cases while maintaining the capability to handle more complex error patterns when needed.
Data Source
AI summary
A method and apparatus for decoding a Low-Density Parity-Check (LDPC) code whereby the apparatus comprises an LDPC decoder comprising variable-node calculation circuitry and check-node calculation circuitry: the check-node calculation circuitry is arranged operably to perform a modulo 2 multiplication on a codeword and a parity check matrix to calculate a plurality of first syndromes in a first-stage state. The variable-node calculation circuitry is arranged operably to perform a bit flipping algorithm to generate variable nodes, and calculate soft bits for the variable nodes in a second-stage state. The check-node calculation circuitry is arranged to perform the modulo 2 multiplication on the variable nodes and the parity check matrix to calculate second syndromes in the second-stage. When second syndromes indicate that the previously generated variable nodes are incorrect, a third stage state is repeated until decoding succeeds or a total number of iterations exceeds a threshold.