LDPC Decoder Scheduling to Avoid Parity Matrix Processing Stalls
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing data processing demands in 5G communication systems require faster decoding of Low Density Parity Check (LDPC) codes to mitigate errors caused by noise in communication channels, as existing methods often result in processing stalls during the decoding process.
Innovation Solution
A decoding apparatus and method that utilize a scheduling table to determine the processing order of rows and columns in the parity check matrix, allowing processing on a second row to commence before all columns in the first row are completed, thereby reducing stalls and enhancing decoding speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If sequential processing of rows in parity check matrix is used, then processing simplicity is maintained, but decoding speed decreases due to processing stalls
Solution Approach 1:
The patent applies dynamics by making the processing order flexible and adaptive rather than fixed. The scheduling table dynamically determines which row to process next based on current processing state, allowing the system to adaptively switch between rows to avoid stalls while maintaining systematic control through the scheduling mechanism
Solution Approach 2:
The patent segments the processing of the parity check matrix into independent row units with specific processing orders. By dividing the matrix processing into discrete row segments with defined dependencies, the system can process rows in optimized sequences without requiring complete sequential execution, thereby improving speed while managing complexity through structured segmentation
2Productivity
If all columns in first row are processed before second row, then processing order is simple, but processing stalls occur reducing productivity
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing the optimal processing order of rows in a scheduling table before actual decoding begins. This preliminary scheduling identifies which rows should be processed first to avoid stalls, allowing the decoder to follow an optimized path without real-time complex decisions, thereby improving throughput while keeping runtime complexity manageable
Solution Approach 2:
The scheduling table acts as an intermediary between the parity check matrix structure and the processing engine. It mediates the processing sequence by providing pre-determined row execution orders that optimize throughput, shielding the processing logic from the complexity of stall avoidance while enabling higher productivity through optimized scheduling
Data Source
AI summary
There is provided a decoding apparatus for decoding a low density parity check (LDPC) code, wherein the decoding apparatus includes a memory a memory configured to store a scheduling table indicating a desired processing order of a plurality of rows included in a parity check matrix and a plurality of columns included in each of the rows of the parity check matrix, and processing circuitry configured to decode the LDPC code based on the scheduling table, the decoding including performing processing on at least one column included in a second scheduled row of the parity check matrix before processing of all columns included in a first scheduled row of the parity check matrix has been completed.