Layered LDPC Decoder Parallelization for Storage Conflict Reduction

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Solution Overview

Problem

Existing LDPC decoders face challenges in achieving high decoding efficiency due to storage access conflicts during iterative decoding, leading to high decoding delay and low throughput, which hinders their ability to meet the requirements of low delay and high throughput in 5G mobile communication systems.

Innovation Solution

A decoder architecture that acquires and processes soft bit information in advance by determining variable node and check node information in subsequent layers before completing the current layer's computation, allowing for parallel processing and reducing dependency on previous layer results, thereby speeding up the decoding process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the standard layered-decoding method is used, then the decoding algorithm is reliable and guarantees BER performance, but storage access conflict occurs in the iterative decoding process, leading to high decoding delay and low throughput rate

Engineering Contradiction:
ImproveBER performanceVSAvoidthroughput rate
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies preliminary action by pre-calculating and storing check node information for subsequent layers before the current layer's computation is complete. The computing unit determines check node information of a (k+1)th layer in advance, before finishing the current kth layer, thereby preparing decoding data ahead of time to avoid storage access conflicts and reduce decoding delay while maintaining reliability

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent transforms the traditional sequential layer-by-layer decoding into a multi-dimensional parallel processing approach. By introducing the layer dimension k and enabling computations across different layers simultaneously, the system breaks the sequential dependency constraint and achieves parallel processing, increasing throughput rate while maintaining the reliability guaranteed by the layered structure

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If the standard layered-decoding method is used, then the decoding algorithm is reliable and guarantees BER performance, but storage access conflict occurs leading to high decoding delay

Engineering Contradiction:
ImproveBER performanceVSAvoiddecoding delay
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The computing unit performs preliminary computation by determining check node information of the (k+1)th layer in advance, before the current kth layer computation is complete. This ahead-of-time preparation eliminates waiting time during iterative decoding and reduces overall decoding delay while preserving the reliable BER performance through the maintained layered decoding structure

Inventive Principle:
Principle #10Preliminary action

3Productivity

If parallel processing is enabled by determining subsequent layer information in advance, then throughput rate and decoding efficiency are improved, but device complexity increases

Engineering Contradiction:
Improvethroughput rateVSAvoiddecoder complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the decoding process into distinct computational stages: acquiring soft bit information for the current layer, determining check node information for the current layer, and pre-determining check node information for subsequent layers. This segmentation allows parallel execution of independent stages while managing complexity through structured organization of the computing unit's operations

Inventive Principle:
Principle #1Segmentation

Data Source

PatentEP3829088B1Decoder, decoding method, and computer storage medium
Publication Date: 2024.01.17 ZTE CORP
  • EP3829088B1 patent drawingFigure 1~2
  • EP3829088B1 patent drawingFigure 3~4
  • EP3829088B1 patent drawingFigure 5~6

AI summary

Disclosed are a decoder, a decoding method and a computer storage medium. The decoder includes least one computing unit configured to: acquire soft bit information to be decoded of a variable node n in a basic matrix; determine whether an amount of decoding iterations i is less than a preset decoding iteration threshold; if i is less than the preset decoding iteration threshold, determine whether an amount of decoding layers k is less than an amount of rows a of the basic matrix; if k is less than a, determine soft bit information in a kth layer according to the soft bit information in a (k-1)th layer, and determine variable node information in a (k+1)th layer according to the soft bit information of the variable node n in the (k-1)th layer; determine check node information in the (k+1)th layer according to the variable node information in the (k+1)th update k to k+1, and re-determine whether k is less than a; and in response to k being greater than or equal to a, update i to i+1, and re-determine whether i is less than the preset decoding iteration threshold, until i is equal to the decoding iteration threshold. Also disclosed are a decoding method and a computer storage medium.