LDPC Decoder Streaming Soft Outputs for Lower Latency
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Solution Overview
Problem
Conventional LDPC decoders require significant latency and chip area due to the need to store and process soft-output values in a different order than they are received, which hinders real-time decoding and increases processing time.
Innovation Solution
The proposed method and apparatus enable LDPC decoding by processing soft-output values as soon as they are generated, using a check-node unit and combiner to update values and determine if they form a valid codeword, with a layered decoding algorithm that processes values in the order they are received, reducing latency and chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional LDPC decoders store and process soft-output values in a different order than received, then decoding accuracy is maintained, but latency and chip area increase significantly
Solution Approach 1:
The patent inverts the conventional decoding approach by processing soft-output values in the order they are received rather than reordering them. This is achieved by configuring the check-node units and combiners to operate on incoming values directly, eliminating the need for large buffer memories and complex reordering logic, thus reducing both latency and chip area while maintaining decoding accuracy
Solution Approach 2:
The patent performs preliminary processing by initiating check-node updates before all soft-output values are fully received. The check-node units begin processing with available values and continue as more values arrive, allowing the decoding process to overlap with the reception process and reduce overall latency without requiring storage of all values beforehand
2Productivity
If all soft-output values are processed before determining valid codeword, then decoding accuracy is ensured, but processing time increases
Solution Approach 1:
The patent implements continuous decoding by allowing the check-node units and combiners to operate continuously as soft-output values arrive. The process does not wait for all values to be received before beginning and continuing processing, maintaining a continuous flow of useful action that increases throughput while reducing processing time
Solution Approach 2:
The patent performs partial processing by determining whether a valid codeword has been formed before all soft-output values are completely processed. The parity-check calculator can declare success early when sufficient check nodes are satisfied, performing less than the maximum possible processing while still achieving the desired outcome, thus increasing throughput
Data Source
AI summary
In one embodiment, a signal-processing receiver has an upstream processor and a low-density parity-check (LDPC) decoder for decoding LDPC-encoded codewords. The upstream processor generates a soft-output value for each bit of the received codewords. The LDPC decoder is implemented to process the soft-output values without having to wait until all of the soft-output values are generated for the current codeword. Further, the LDPC code used to encode the codewords is arranged to support such processing. By processing the soft-output values without having to wait until all of the soft-output values are generated for the current codeword, receivers of the present invention may have a lower latency and higher throughput than prior-art receivers that wait until all of the soft-output values are generated prior to performing LDPC decoding. In another embodiment, the LDPC decoder processes the soft-output values as soon as, and in the order that, they are generated.