LDPC Decoder Architecture With Parallel Sub-Matrix Pipelining
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Solution Overview
Problem
Current communication systems employing LDPC codes face challenges in achieving low bit error rates at high data rates due to latency constraints with traditional concatenated codes, limiting their application in high-speed communication systems.
Innovation Solution
A novel LDPC decoder architecture that utilizes cyclic shifted identity sub-matrices and permuted identity sub-matrices to enable accelerated decoding performance, allowing for pipelined processing with minimal coding gain loss, thereby increasing throughput and reducing hardware footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional concatenated codes are used, then error correction capability is maintained, but latency increases and throughput decreases
Solution Approach 1:
The LDPC code is divided into multiple sub-codes, each corresponding to a specific sub-matrix in the parity check matrix. This segmentation allows parallel processing of different sub-codes simultaneously, increasing throughput while maintaining error correction capability. The decoder processes multiple sub-codes in parallel rather than sequentially processing traditional concatenated codes.
Solution Approach 2:
The patent introduces a new dimensional structure by organizing the LDPC code into a multi-dimensional array structure with sub-matrices arranged in rows and columns. This dimensional organization enables pipelined processing where different stages can work on different sub-matrices simultaneously, reducing latency and increasing throughput compared to traditional one-dimensional concatenated code processing.
2Productivity
If accelerated decoding is implemented, then throughput increases, but hardware complexity increases
Solution Approach 1:
The patent merges multiple processing functions into unified hardware blocks. The check node processing and bit node processing are combined in an integrated decoder architecture that shares common resources such as memory structures and computational units across different sub-codes, reducing overall hardware footprint while maintaining accelerated throughput.
Solution Approach 2:
The decoder architecture employs universal processing units that can handle multiple sub-codes and different types of operations. The same hardware blocks are reused across different iterations and sub-code processing, eliminating the need for dedicated hardware for each sub-code and reducing overall hardware complexity while enabling parallel accelerated decoding.
3Reliability
If more iterations are performed, then coding gain increases, but decoding time increases
Solution Approach 1:
The patent performs preliminary processing by organizing the parity check matrix into sub-matrices and pre-computing syndrome values for each sub-code. This preliminary action allows the main decoding iterations to converge faster because the initial setup has already extracted useful information, reducing the number of full iterations needed to achieve the same coding gain and thereby reducing total decoding time.
Solution Approach 2:
The pipelined architecture ensures continuous useful action by overlapping the execution of different iterations. While one iteration is completing its check node processing, another iteration is simultaneously performing bit node processing, and a third is beginning syndrome calculation. This continuity maintains coding gain convergence while reducing wall-clock decoding time through efficient resource utilization across iterations.
Data Source
AI summary
Accumulating LDPC (Low Density Parity Check) decoder. The accumulating decoding architecture described herein is applicable to LDPC codes operating on a parity check matrix, H, consisting of CSI (Cyclic Shifted Identity) sub-matrices (or matrix sub-blocks) or permuted identity sub-matrices (or matrix sub-blocks). In such a structure, the entire LDPC matrix is broken into square sub-matrices such that each sub-matrix consists of either a CSI sub-matrix or a permuted identity sub-matrix, or a null matrix. The iterative decoding process operates by updating of APP (a posteriori probability) or gamma (γ) values and check edge message (λ) values, and this by updating one or more individual rows within a number of sub-matrix rows (or all sub-matrix or sub-block rows) are processed in parallel. The amount of parallelism is specified by the designer and is typically an integer divisor of the sub-matrix (or sub-block) size.