LDPC Decoder Syndrome Memory for Lower Iteration Overhead

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Solution Overview

Problem

Conventional LDPC decoders are inefficient due to the need to reset and recalculate syndrome results each iteration and must read/write to memory whether bits are flipped, leading to unnecessary overhead and power consumption.

Innovation Solution

An LDPC decoder configuration that includes a first syndrome memory for storing previous iteration results and a second syndrome memory for updating current results, allowing bit flipping based on parity-check equations without resetting syndrome results, and only reading/writing to memory when bits are flipped.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional LDPC decoders reset and recalculate syndrome results each iteration, then the decoding process can be completed, but the decoding efficiency is low and unnecessary overhead is generated

Engineering Contradiction:
Improvedecoding efficiencyVSAvoiditeration overhead
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-calculating and storing syndrome results from previous iterations in a syndrome memory before the current iteration begins. This allows the decoder to reuse previously computed syndrome information without resetting and recalculating from scratch, thereby reducing iteration overhead and improving decoding efficiency.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses copying by creating a copy of the syndrome results from the previous iteration and storing them in a dedicated syndrome memory. This copied syndrome information is then reused in the current iteration, eliminating the need to recalculate and reducing the time loss associated with redundant computations.

Inventive Principle:
Principle #26Copying

2Ease of operation

If conventional LDPC decoders read and write to memory for every bit operation, then bit flipping can be performed, but power consumption is high

Engineering Contradiction:
Improvebit flipping capabilityVSAvoidpower consumption
Core Design Contradiction:
Ease of operationVSUse of energy by moving object

Solution Approach 1:

The patent extracts and separates the syndrome calculation function from the main decoding loop by implementing a dedicated syndrome memory that stores pre-calculated syndrome results. This extraction allows the decoder to avoid repeated memory read/write operations for syndrome calculations, reducing power consumption while maintaining bit flipping capability.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The syndrome memory serves itself by automatically storing and retaining syndrome results from previous iterations, making this information readily available for future iterations without requiring repeated computation or memory access. This self-service mechanism reduces the energy required for syndrome management during decoding operations.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS8677225B1Low-density parity-check decoder
Publication Date: 2014.03.18 MARVELL ASIA PTE LTD
  • US8677225B1 patent drawing
  • US8677225B1 patent drawing
  • US8677225B1 patent drawing

AI summary

This disclosure describes a low-density parity-check (LDPC) decoder that is configured to decode a codeword using an iterative process. The decoder includes a memory to store the codeword and a first syndrome memory configured to store a syndrome result determined in a previous iteration. The decoder further includes circuitry to flip bits of the codeword based on the syndrome result and one or more parity-check equations, and a second syndrome memory configured to update a current syndrome result during a current iteration based on the bits of the codeword that are flipped by the circuitry.