LDPC Decoder Architecture With Incremental Syndrome Updates
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Solution Overview
Problem
The increasing bit error rate in memory devices due to higher memory integration and bit density is not adequately addressed by traditional error correction algorithms like BCH, leading to inefficiencies in data reliability and longer decoding times with LDPC algorithms.
Innovation Solution
A decoder architecture that performs real-time syndrome updates and incremental check calculations using a current and previous syndrome to determine error symbols, reducing decoding time and avoiding redundant iterations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional BCH error correction algorithm is used, then device complexity is low, but reliability of data correction is insufficient for high bit error rates
Solution Approach 1:
The decoder is divided into multiple independent processing units including a syndrome calculator, iterative processor, and error correction unit. Each unit handles specific tasks in the decoding process, allowing parallel processing and improving reliability without requiring a complete redesign of the entire system.
Solution Approach 2:
The decoder implements dynamic iterative processing where the number of decoding iterations is adjusted based on the actual bit error rate conditions. The system can adaptively increase or decrease iteration counts, and switch between different decoding strategies (LDPC vs. BCH) depending on the error severity, optimizing both reliability and resource usage.
2Reliability
If LDPC algorithm is used to improve error correction capability, then reliability is improved, but decoding time increases due to multiple iterations
Solution Approach 1:
The system performs a limited number of iterative decoding operations rather than exhaustive processing. It uses a preset maximum iteration count and early termination conditions, performing only the necessary iterations required to correct the actual error level present in the data, thus reducing unnecessary decoding time while maintaining correction capability.
Solution Approach 2:
The decoder implements feedback mechanisms where the syndrome calculation results from each iteration are used to determine whether to continue or terminate the decoding process. If the syndrome becomes zero or error correction converges within the preset iteration limit, the process terminates early, significantly reducing decoding time for low error rate scenarios.
3Productivity
If memory integration and bit density are increased, then productivity is improved, but bit error rate increases
Solution Approach 1:
The system dynamically adjusts decoding parameters including iteration count, threshold values, and algorithm selection based on the actual bit error rate conditions detected in the data. This allows the decoder to optimize its performance for different memory integration levels and error conditions, maintaining reliability despite increased bit density.
Data Source
AI summary
The present disclosure disclose decoders, decoding methods, memory systems, memory controllers and computer readable storage medium. The decoder comprises a first data processing circuit and a second data processing circuit coupled to the first data processing circuit; the first data processing circuit is configured to: perform a current check calculation using a current column of a check matrix and a current sub-matrix of a current flag matrix, and perform a current incremental check calculation on a result of the current check calculation and a previous syndrome to generate a current syndrome; the second data processing circuit is configured to: determine an error symbol in a next data block of the codeword, using one of the current syndrome or a previous syndrome and a next column of the check matrix, based on the current syndrome not satisfying a check condition; wherein the previous syndrome is generated prior to the current syndrome.