LDPC Decoder Check-Node Switching for Trapping Set Errors

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Solution Overview

Problem

Low-density parity-check (LDPC) decoders face challenges in error-floor characteristics due to trapping sets, which can lead to incorrect decoding results, and existing techniques may not effectively address these issues across varying operating conditions.

Innovation Solution

The method involves selecting a scaling factor and an offset value to generate scaled-and-offset messages for error-correction decoding, using a controller to adjust these parameters in an LDPC decoder, which can change the check-node algorithm to break dominant trapping sets, thereby improving error-floor characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a fixed check-node algorithm is used in the LDPC decoder, then the decoding process is simple and fast, but the decoder cannot effectively break trapping sets and suffers from poor error-floor characteristics

Engineering Contradiction:
Improveerror-floor characteristicsVSAvoiddecoder structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements dynamic check-node algorithms by introducing multiple update rules (min-sum, max-product, offset min-sum) that can be selectively applied during decoding iterations. The controller dynamically switches between different update rules based on iteration count and message characteristics, allowing the decoder to adaptively break trapping sets while maintaining a relatively simple overall structure.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes algorithmic parameters by introducing offset values and scaling factors that modify the check-node update equations. These parameter adjustments transform the standard min-sum algorithm into offset min-sum and scaled versions, enabling the decoder to overcome trapping sets without requiring a complete structural redesign.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If multiple check-node algorithms are implemented to break trapping sets, then error-floor characteristics improve, but the decoder complexity increases

Engineering Contradiction:
Improvedecoding accuracyVSAvoidcheck-node unit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the check-node processing into distinct functional units: message reception modules, update rule selection logic, offset addition modules, and message transmission modules. Each segment performs a specific function, and the modular architecture allows multiple algorithms to coexist without creating a monolithic complex structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The check-node unit is designed with multi-functionality to execute different update rules (min-sum, max-product, offset min-sum) using the same hardware resources. The controller selects which algorithm to apply based on current decoding conditions, allowing one structural unit to serve multiple algorithmic purposes and reducing overall complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If offset values and scaling factors are adjusted to address trapping sets, then decoding performance improves, but the control logic becomes more complex

Engineering Contradiction:
Improvetrapping set resolutionVSAvoidcontroller logic
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies periodic action by adjusting offset values and scaling factors at regular intervals (e.g., every 10 iterations or at specific iteration milestones). This periodic parameter adjustment allows the controller to systematically address trapping sets without requiring continuous complex control logic, simplifying the overall control architecture.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS8316272B2Error-correction decoder employing multiple check-node algorithms
Publication Date: 2012.11.20 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US8316272B2 patent drawing
  • US8316272B2 patent drawing
  • US8316272B2 patent drawing

AI summary

In one embodiment, an LDPC decoder has a controller and one or more check-node units (CNUs). The CNUs generate check-node messages using a scaled min-sum algorithm, an offset min-sum algorithm, or a scaled and offset min-sum algorithm. Initially, the controller selects a scaling factor and an offset value. The scaling factor may be set to one for no scaling, and the offset value may be set to zero for no offsetting. If the decoder is unable to correctly decode a codeword, then (i) the controller selects a new scaling and/or offset value and (ii) the decoder attempts to correctly decode the codeword using the new scaling and/or offset value. By changing the scaling factor and/or offset value, LDPC decoders of the present invention may be capable of improving error-floor characteristics over LDPC decoders that use only fixed or no scaling factors or fixed or no offsetting factors.