LDPC Decoder Traversal Architecture for Lower Hardware Use
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Solution Overview
Problem
Existing LDPC code encoders and decoders require a fully parallel architecture that consumes a large amount of hardware resources, making them inefficient in terms of resource usage.
Innovation Solution
A data processing apparatus with m data processing modules that process n operations in a sequential manner, where m < n, allowing for reuse of modules over time to reduce hardware resource consumption, and an LDPC decoder with a variable node processing unit, check node processing unit, and memory for iterative decoding, where messages are computed and updated in a traversing manner to optimize resource use.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a fully parallel encoder architecture is used to compute the product of data and generator matrix, then the encoding speed and throughput are improved, but the hardware resource consumption increases significantly
Solution Approach 1:
The encoder divides the n-column generator matrix processing into multiple segments, with each data processing module responsible for a subset of columns. Instead of using n parallel modules for all columns, the system uses m modules (where m < n) that process different column segments at different times, reducing hardware resources while maintaining encoding capability
Solution Approach 2:
The encoder employs periodic time-division multiplexing where m data processing modules alternate processing different column segments of the generator matrix. Each module processes Ni columns in the i-th period following a calculation sequence, creating a periodic pattern of operations that reduces peak hardware requirements while maintaining throughput
2Productivity
If a fully parallel decoder architecture is used to process variable nodes and check nodes simultaneously, then the decoding speed is improved, but the hardware resource consumption increases significantly
Solution Approach 1:
The decoder segments the variable nodes and check nodes into groups that can be processed sequentially by a smaller number of processing units. Instead of having parallel processing units for every node, the system divides the Tanner graph into manageable segments that can be traversed and processed in organized passes, reducing the number of simultaneous processing units needed
Solution Approach 2:
The decoder implements periodic iterative decoding where variable node processing and check node processing are performed in alternating passes. Each iteration traverses the Tanner graph in a systematic sequence, processing different node types in periodic cycles rather than simultaneously, which reduces peak hardware requirements while maintaining decoding performance
Data Source
AI summary
Disclosed relates to a decoder for LDPC code, including: a variable node processing unit; a check node processing unit; a memory for storing iterative messages of edges of a parity-check matrix for LDPC code; and a controller for controlling the node processing units to perform iterations of decoding until the decoding ends, wherein, in each iteration of decoding, the controller controls the variable node processing unit to compute variable node messages in a traversing manner for all variable nodes and updates the iterative messages in the memory according to the computed variable node messages, and controls the check node processing unit to compute check node messages in a traversing manner for all check nodes and updates the iterative messages in the memory according to the computed check node messages.