LDPC Decoder Time-Division Multiplexing for Variable Block Lengths
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Solution Overview
Problem
Existing decoder designs face inefficiencies and increased costs when supporting error correcting codes with vastly different block lengths, as separate decoders for each length require more silicon area and longer development times, while multiplexing codes becomes inefficient when block lengths vary significantly.
Innovation Solution
The proposed solution involves using time-division multiplexing of decoding logic to allow a single decoder to efficiently support multiple block lengths by spreading the decoding of larger codewords into multiple time slots, without compromising error correction performance, thus enabling the use of optimal LDPC codes for different block lengths with low time to market and low cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate decoders are used for each code length, then decoding performance is optimized for each specific block length, but silicon area and development time increase significantly
Solution Approach 1:
The patent implements a universal decoder architecture that can decode multiple LDPC codes with different block lengths using the same hardware structure. The decoder supports codes with block lengths ranging from 512 bits to 4096 bits by dynamically configuring the parity-check matrix dimensions and processing iterations, eliminating the need for separate dedicated decoders for each code length while maintaining optimal decoding performance for each specific code.
Solution Approach 2:
The decoder employs dynamic configuration capabilities where the parity-check matrix size, number of processing units, and iteration count are adaptively adjusted based on the input code length. This dynamic reconfiguration allows the same hardware to optimize its operation for different code lengths, achieving near-optimal performance for each specific block length without requiring static dedicated hardware for each case.
2Area of stationary object
If multiplexing codes in the decoder is used, then silicon area is reduced, but decoding efficiency decreases when block lengths vary significantly
Solution Approach 1:
The patent segments the decoding process into multiple processing units that can be dynamically activated based on the code length. For longer codes, more processing units are engaged, while for shorter codes, fewer units are used. This segmentation allows efficient utilization of silicon area while maintaining high decoding efficiency across different block lengths, avoiding the performance degradation associated with traditional multiplexing approaches.
Solution Approach 2:
The decoder dynamically changes key parameters including the parity-check matrix dimensions, number of processing iterations, and processing unit activation based on the input code length. This parameter adaptation ensures that the decoder maintains high efficiency for each specific block length while using a single unified hardware structure, thereby achieving both area reduction and sustained productivity.
3Device complexity
If a single decoder supports multiple block lengths, then device complexity is reduced, but adapting to different code lengths becomes more challenging
Solution Approach 1:
The patent employs systematic parameter change mechanisms where the decoder configuration (parity-check matrix size, processing units, iterations) is adaptively adjusted based on the detected code length. This parameter flexibility allows a single relatively simple decoder architecture to support a wide range of block lengths from 512 to 4096 bits, resolving the contradiction between simplicity and adaptability.
Solution Approach 2:
The decoder is designed with universal functionality to handle multiple code lengths through a unified architecture. By incorporating configurable components that can be dynamically sized and configured, the single decoder achieves multi-functionality, supporting various LDPC codes without requiring complex dedicated hardware for each code length, thus balancing device complexity with versatility.
Data Source
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AI summary
Examples relate to a decoding apparatus, a decoding device, a decoding method, a decoding computer program, and a communication device, a memory device and a storage device comprising such a decoding apparatus or decoding method. A decoding apparatus for performing iterative decoding on a codeword comprises processing circuitry comprising a plurality of processing units, and control circuitry configured to control the iterative decoding of the codeword. The iterative decoding is based on a parity-check matrix. The matrix is sub-divided into two or more partitions. The control circuitry is configured to operate in a first mode of operation to process a codeword having a first length, and to operate in a second mode of operation to process a codeword having a second length. The control circuitry is configured to multiplex the utilization of the plurality of processing units across the two or more partitions of the matrix at least in the second mode of operation.